Lesson 1 — The buck converter: what happens, why, and how to design it

Power Electronic Systems · HTWG · 2026
Teaching source: lecture 1, Anwendungen der Leistungselektronik, WS 2025/2026, Riccardo Tinivella / Kurt Schenk.
Prerequisite: the 2026 circuit-foundations recap. Language: English, following the intro lesson.

A converter design starts with a question, not a component value. What must the circuit do? Which physical limit matters first? We will use the answer to choose each part, then check whether the choice works.

Our example is TI's PMP31349 reference design. This synchronous GaN buck converts a 30–60 V bus to 12 V at 20 A. An LM5148 peak-current-mode controller drives an LMG2100R044 half-bridge at 350 kHz.

We start from the specification and work towards a complete design. At each step, we compare our estimate with TI's chosen part and published measurements.

How we work. First, estimate by hand. State the assumptions and predict what the circuit should do. Then simulate the same model and compare the results. Finally, compare with TI's measurements and explain any gap.

A failed choice is useful evidence. We keep it on the page, marked No!, and explain what must change. Before moving on, explain why we chose this option. Name its main benefit and cost. Then say when a credible alternative would become preferable.

This sequence follows C. Basso, Switch-Mode Power Supplies: SPICE Simulations and Practical Designs, McGraw-Hill, 2008, §5.1. The worked examples are our own. The Example scripts reproduce the calculations. §9 explains the two PLECS models to draw.

Where the buck is used. The German name says what the buck can do: Tiefsetzsteller, the converter that only sets the voltage lower. Its output must stay below its input. The boost of a later lesson is the Hochsetzsteller.

Use a buck when the load needs a lower voltage and galvanic isolation is unnecessary. Applications range from small point-of-load regulators to high-current stages with several phases. Switching frequencies span roughly 20 kHz to 10 MHz. A few hundred kilohertz is common.

Efficiency depends on the complete design and operating point. PMP31349 reaches 95.5 % at 48 V and 20 A (TI, measured, §8).

Reading route. Follow Part I (§1–11) for the complete design. Use Part II (§12) to practise diagnosing a waveform, choosing a model and defending a decision. The appendices hold background and longer derivations. §13 gives the sources and numerical checks.

The recap supplies the circuit foundations. Return to it when a current path, RMS calculation or balance equation is unclear.

Learning outcomes and teaching route

By the end, students should be able to:

• write a converter specification and say which limits are given and which are their own
• derive the conversion ratio from volt-second balance and find the duty-cycle extremes
• size $L$, $C_{\mathrm{out}}$ and $C_{\mathrm{in}}$ from ripple, load-step and RMS limits
• check the chosen values against real parts with DC-bias derating, ESR and saturation
• calculate mean and RMS stresses with the correct current measure for each loss
• explain how dead time and the sign of the valley current shape each GaN switching edge
• read a current-mode loop gain and say which input sets its crossover and phase margin
• estimate losses and junction temperature from datasheets, and say what a calibration against measurement adds
• predict what changes in critical conduction, discontinuous conduction, at another switching frequency or with another LC filter
• explain why a fixed-duty CCM buck does not regulate current, and evaluate sensitivity at a stated operating point (Part II).

Lesson 01 spans three sessions of 90 minutes. Students read the rest at home: the appendices, and the Part II exercises that the sessions do not work.

1. A 12 V, 20 A synchronous GaN buck from a 30–60 V source

A 48 V battery bus must supply a 12 V, 20 A load. TI's PMP31349 does it with an LM5148 controller in peak current mode and forced PWM, driving an LMG2100R044 GaN half-bridge. We take TI's published operating range as given. Where TI publishes no limit, we set our own target and mark it as ours.

Ours or TI. Every number in Part I carries one of two labels. Ours is computed from this specification and from datasheets. TI is a part TI chose or a value TI measured, taken from the TIDT427A test report, the TIDMDL2 schematic and the TIDMDL6 bill of materials.

The Example scripts in ti-pmp31349/scripts/ compute every ours number and write it to a *-checks.json file, which this text quotes. Never mix the two labels: a curve fitted to TI's measurement is not our prediction.

Design sequence. Start with the duty range (§2). Then choose the inductor (§3), output capacitor (§4) and input capacitor (§5). Check the power stage (§6), loop (§7), losses and temperature (§8). In §9, compare the complete model with measurements.

Each step starts with our estimate. We then compare it with TI's choice and use TI's actual part in the next step. This keeps the final model comparable with the measured board. All current ripple values are peak to peak unless labelled RMS.

Before choosing parts. We keep TI's published voltage, current and frequency as constraints. Ripple and transient limits are ours. Tightening one may require more hardware or a different loop. Change a target openly, then repeat the affected checks.

2. Duty-cycle extremes

2.1 Two switch positions, two ramps

In the synchronous buck the high-side switch connects the switch node to $V_{\mathrm{in}}$ for the time $DT_s$. The low-side switch then clamps the node to ground for $(1-D)T_s$. §4 checks that the output voltage barely moves within one period. The inductor then sees two constant voltages, and its current is two straight lines:

The inductor resists a change of current, not current itself. While the low side conducts, the current still flows toward the load and the inductor releases energy. The output capacitor takes the difference, $i_C = i_L - i_o$. The output ripple is therefore a consequence of the inductor ripple, and §4 checks it after we choose the capacitor.

2.2 Volt-second balance sets the duty

Repeating the two intervals at $f_s = 1/T_s$, with duty ratio $D = t_{\mathrm{on}}/T_s$, is pulse-width modulation. At start-up $V_o$ is small: the current rises steeply and falls slowly, so it grows from period to period and charges the output. As $V_o$ rises the two ramps come into balance.

In periodic steady state the inductor current returns to its starting value, so the volt-seconds across L cancel over one period. The recap derives this from periodicity (§7.2) and applies it to the ideal buck (§7.3). The cycle average of the inductor voltage is zero, not its instantaneous value.

With $V_o$ regulated, the duty follows the input. The extremes sit at the ends of the input range:

2.3 What each current does, and why the ideal buck is lossless

With ideal switches and small output ripple, every current in the stage is a piece of the inductor current or zero:

The input voltage is constant, so the input power is $V_{\mathrm{in}}$ times the mean input current: $P_{\mathrm{in}} = V_{\mathrm{in}}\cdot D\cdot I_o = V_o\cdot I_o = P_o$. The ideal buck is a DC transformer with ratio D: it steps the voltage down and the mean current up, and it loses nothing. The losses of §8 come from the components, not from the principle.

What the extremes decide. At 60 V, $D_{\min}$ gives the shortest on-time and the largest inductor ripple (§3). The low side conducts for 80 % of the period, so it has the larger conduction loss (§8).

At 30 V, $D_{\max}$ = 0.400 is closest to 0.5. This gives the largest input-capacitor RMS current within our input range (§5). Different checks have different worst cases.

TI chose, TI measured. TI chose the 30–60 V range and the 12 V output, so the extremes follow directly. On the board, the conduction and dead-time losses push the duty slightly above the ideal $D = V_o/V_{\mathrm{in}}$.

Our datasheet loss model with TI's parts needs $D$ = 0.2565 at 48 V and 20 A (ours, loss-estimate-checks.json). §8.2 shows where the extra duty goes. TI measured the switching frequency at 344.9 kHz rather than 350 kHz (TIDT427A fig. 3-2). We keep TI's range and $f_s$ and continue with the inductor.

What we can choose. The required voltage ratio fixes the ideal duty. We cannot lower duty independently and keep the same output. A different bus voltage is an alternative system choice. It changes ripple, timing and device stress together.

3. The inductor

3.1 The ripple ratio sets L

Integrate either ramp of §2.1 over its own interval and substitute $D = V_o/V_{\mathrm{in}}$:

At fixed $V_o$ the ripple grows with $V_{\mathrm{in}}$, so the worst case is the maximum input, 60 V. A shortcut warning: $V_{\mathrm{in}}\cdot D(1-D)$ peaks at $D$ = 0.5 only if $V_{\mathrm{in}}$ stays fixed while $D$ changes. Here $V_o$ stays fixed and $V_{\mathrm{in}}$ sweeps, so $V_{\mathrm{in}}$ and $D$ are coupled. Find the worst case from the equation above, not from $D(1-D)$.

We ask for a ripple of $r$ = 0.30 of the full load at 60 V. Solving for L:

So our inductor is 4.571 µH (ours). This is an ideal minimum: it carries no allowance for tolerance or for the drop of inductance with current. The ripple ratio is a full-load specification: at a 2 A load the same ripple is three times the load current. Always state the ripple against full load.

3.2 Peak and RMS current, with the right measure

We now take TI's 4.7 µH and evaluate it at the worst case, 60 V:

That is a ripple of 5.836 A and a peak of 22.92 A (ours, TI's part). Which current measure enters a loss depends on the element, as the recap derives (§6.1, §6.2):

Never use the mean current for a resistive loss. It is the most common error in loss estimates.

Two rules from the recap (§5.1–5.2) give every current of the stage without new integrals. Compressing a waveform into the fraction $D$ of the period, with zero elsewhere, multiplies its mean by $D$ and its RMS value by $\sqrt{D}$. Orthogonal parts, such as DC and a zero-mean triangle, add in mean square. With $J = I_o^2 + \Delta I_L^2/12 = I_{L,\mathrm{rms}}^2$:

At this ripple ratio the RMS current is only slightly above the 20 A mean. The DC term dominates every conduction loss. The low side conducts for $1-D$ of the period, so it carries most of that loss.

3.3 Checks against the real part

• Saturation. Würth specifies a 10 % drop of inductance at 20.9 A (reverse-engineering-checks.json, datasheet). Our 22.92 A peak at 60 V and full load lies past that point, so the strict rule "peak below the saturation current" fails: No! The metal-composite core loses inductance gradually. The cost is therefore a slightly larger ripple than (3.2b), not a collapse. TI's schematic notes "~24 A Ipk" for this inductor, close to our 22.92 A.
• Current limit. TI sets the peak current limit at 35 A (TIDMDL2 note: 60 mV across the 1.714 mΩ shunt). That leaves headroom for the load step, but in an overload the inductor sees 35 A, far past 20.9 A. Always check the inductor at the current limit, not only at full load.
• Heating. The BOM lists the part as a 17 A, 3.85 mΩ inductor (TIDMDL6). At 20.07 A RMS it runs above that rating. TI measured 95 °C on the inductor at 20 A with a heat sink fitted (TIDT427A §2.3.2).
• Slew rate. A larger L lowers the ripple but also the current slew rate the controller can command, $(V_{\mathrm{in}}-V_o)/L$, which limits the load-step response (§7.3).

TI chose, TI measured. TI chose a 4.7 µH Würth 74439370047 (WE-XHMI, shielded metal composite). Our ripple ratio of 0.30 at 60 V asks for 4.571 µH. TI's 4.7 µH is a standard value just above it. The ripple at 60 V, 5.836 A, is therefore slightly below our target.

TI did not measure the inductor current. §9 checks the ripple it causes at the output and the input. From here on the lesson continues with TI's 4.7 µH.

3.4 What if we allow 10% or 100% current ripple?

Our 30% target is a design choice. To see its consequences, compare two extremes. Here ripple means peak-to-peak inductor current divided by the 20 A full-load current. It is not duty ratio. Keep 60 V input, 12 V output and 350 kHz fixed. Use the ideal CCM equations of §3.1–3.2.

Before calculating, predict which choice needs more inductance. Which one gives the capacitor more work?

Choose 10% when ripple-current stress matters. Peak current and capacitor RMS current are lower. The cost is ten times more inductance. At the same applied voltage, current changes ten times more slowly. Check the load-step response before accepting that cost.

Choose 100% when less inductance and faster current change justify the ripple. The capacitor carries ten times more RMS ripple current, and the inductor must handle a 30 A peak. This remains CCM at full load: the valley is still 10 A. It is not boundary conduction.

Less inductance does not by itself guarantee a smaller or more efficient part. Compare actual saturation curves, winding and core losses, capacitor losses and transient response. With diode emulation, reduced load can also move the high-ripple design into DCM sooner.

Our decision. Keep 30% for the base design and continue with TI's 4.7 µH. The 100% alternative requires relaxing that ripple target. The 10% alternative reduces ripple, but its larger inductance still needs a transient check. Neither alternative is a qualified replacement part.

Your choice. Suppose capacitor ripple-current capability is the limiting constraint. Which direction would you try first? Now suppose current rise is too slow during a load step. Explain what you would change and which earlier check you must repeat.

scripts/ripple_tradeoff.py writes data/ripple-tradeoff.json. It checks the table against independently integrated current ramps, including mean/RMS current, capacitor charge and ideal power balance.

4. The output capacitor

4.1 Charge balance

The capacitor has the dual property of the inductor. In periodic steady state the charge delivered to a capacitor equals the charge removed, so its mean current is zero (recap §7.2).

The output capacitor carries the ripple of the inductor current. It cannot supply a lasting DC deficit without its voltage drifting. Only the loop can correct that.

4.2 The ripple-only choice

In CCM the capacitor current is a zero-mean triangle of height $\Delta I_L$. The capacitor charges while that current is positive, for half a period. The charge is a triangle of base $T_s/2$ and height $\Delta I_L/2$, so $\Delta Q = \Delta I_L\cdot T_s/8$. For an ideal capacitor:

Our ripple limit alone asks for 17.37 µF (ours).

4.3 The load step: No!

When the load jumps by $\Delta I_{\mathrm{step}}$, the inductor current cannot follow at once. Until the loop answers, roughly for $1/(2\pi f_c)$, the capacitor supplies the deficit. Holding the drop within $\Delta V_{\mathrm{step}}$ at our crossover target needs:

17.37 µF against 126.3 µF: the ripple-only choice fails the load step by more than a factor of seven. No! The load step, not the ripple, sizes this bank.

Never accept a capacitor because the ripple is small. Steady switching ripple proves nothing about transient droop, about the effective capacitance under bias, about RMS heating or about high-frequency behaviour. A load step removes charge in proportion to the integral of the current deficit, and the loop decides how long that deficit lasts.

4.4 Real parts: DC bias, then ESR — No! again

We take 126.3 µF as the minimum effective capacitance. TI uses four 22 µF 25 V X7R ceramics and two 150 µF 16 V tantalum polymers (TIDMDL6). By our DC-bias estimate, each ceramic keeps about 10 µF at 12 V (ours). The bank therefore gives ≈340 µF and passes (4.2b).

A capacitor helps the loop only while it still looks capacitive at crossover. Its ESR must therefore stay below its reactance at $f_c$:

Kemet rates the polymer at 65 mΩ ESR maximum per part (T598D157M016ATE065). Two in parallel give 32.5 mΩ, more than twice the 13.37 mΩ budget of the whole 340 µF. No!

Which branch sets the impedance where? At $f_c$ the ceramic branch still shows $|Z|$ ≈ 114 mΩ, so it does not help there. The polymer ESR sets the impedance of the bank. Its zero lies at

below our 35 kHz target. At crossover the output stage therefore looks resistive, and the compensation must account for it (§7). The ceramics are useful near $f_s$. At 350 kHz their branch shows $|Z|$ ≈ 11.4 mΩ, lower than the polymer ESR. They therefore carry most of the ripple current and bypass the ESL of the polymers. Without them the ESR term alone would be

That is 190 mV (ours), above our 120 mV limit. The ESR also reshapes the ripple and adds a zero to the loop, so never judge a capacitor by the size of its ripple alone.

What a failed ESR check means. Check (4.3a) assumes we want a capacitive bank at $f_c$. When it fails, two redesigns remain. The first adds low-ESR capacitance until the ESR of the bank drops below 13.37 mΩ. The second keeps the bank, lowers the crossover and compensates the ESR zero.

TI's board matches the second route: it crossed at about 15 kHz (TI measured, §7). At that crossover (4.2a) asks for ≈290 µF, and TI's 340 µF passes it (loop-checks.json).

Decision: keep TI's bank. The bank passes the capacitance check but fails the ESR check, so the compensation must include the 16.3 kHz ESR zero (§7). TI measured 56 mV peak-to-peak output ripple at 48 V and 20 A (TIDT427A fig. 3-5). The 10 → 20 A load step gave a −276 mV dip (fig. 3-7). Both meet our targets, and the bank keeps the model comparable with the board. A different bank changes ripple and ESR, so it needs a new loop calculation.

5. The input capacitor

The stage draws the inductor current from the input while the high side conducts, and nothing while the low side conducts. If the source behind the input filter supplies only the mean $D\cdot I_o$, the local capacitor supplies the difference $(1-D)\cdot I_o$ during $DT_s$. The charge it loses is a rectangle, $\Delta V = I\cdot t_x/C$:

Our input-ripple target asks for 10.71 µF (ours). No inductor smooths this current: the capacitor itself is the filter, which is why the input ripple is volts while the output ripple is millivolts.

The same pulsed current sets the RMS stress. Neglecting the inductor ripple, and with the source supplying only the mean:

$D(1-D)$ peaks at $D$ = 0.5, and over our range $D_{\max}$ = 0.400 at 30 V lies nearest to it. The output bank carries only the ripple triangle, $\Delta I_L/\sqrt{12}$. The input bank carries a pulsed current of about half the load. Always size input capacitors for RMS current at the duty nearest 0.5, not at nominal input.

Decision. Our 1.0 V ripple target at 48 V needs 10.71 µF. TI uses seven 4.7 µF, 100 V X7S ceramics (TIDMDL6). Their nominal capacitance is not the value available under bias.

TI's schematic notes "1.5 µF effective @ 48 Vin" over the bank. We interpret that as a per-part value: 7 × 1.5 µF = 10.5 µF. This is just below our requirement. Ahead of this bank, TI places a 5.6 µH filter inductor and a 47 µF hybrid polymer. A 0.5 Ω resistor damps that filter (TIDMDL2).

TI measured 1.28 V peak to peak at 48 V and 20 A (TIDT427A fig. 3-6). No! This exceeds our 1.0 V target. TI publishes no input-ripple limit, so this is a failure against our target. §9 shows that the measurement implies only ≈8.8 µF effective. We retain ≈10.5 µF in the model and keep this discrepancy visible.

If 1.0 V is mandatory, revise the bank. More effective local capacitance is the first candidate. Nominal microfarads alone are not sufficient under bias. Recheck impedance and RMS current. A relaxed target avoids that redesign only if the system permits it.

6. The power stage: GaN half-bridge and dead time

6.1 The half-bridge and its dead time

The LMG2100R044 puts both GaN switches and their drivers in one package (SNOSDF9B). Our model uses 4.4 mΩ typical on-resistance, multiplied by 1.4 for the hot device. The low side replaces the diode of the classical buck (Appendix D), so the conduction drop at 20 A is a resistance, not a junction.

The two switches must never conduct together. The LM5148 holds both off for a dead time $t_d$ at each edge, adaptive and 20 ns typical (SNVSC01 §7.5). During $t_d$ the inductor keeps its current flowing. The low-side GaN conducts it in reverse, in the third quadrant, with a drop $V_{SD}$ of about 1.5 V.

SNOSDF9B gives this value as typical at 0.5 A reverse current and publishes no value at 20 A. The drop at 20 A is likely higher, so (6.1b) is probably a low estimate. GaN has no body diode and so no reverse-recovery charge. What remains is this third-quadrant drop, paid at both edges:

6.2 Which device switches at zero, and at which edge

Resonant converters were the first answer to switching loss. Today, soft switching does the same where possible: the circuit and its timing bring the voltage or the current to zero at the transition. Zero inductor current, zero device current and zero device voltage are different conditions.

ZCS means negligible current through the device at its switching event. ZVS means negligible voltage across it, usually at turn-on. Name the device and the edge before calling a transition soft.

At 48 V TI's 4.7 µH ripples by 5.47 A (ours). The sign of the valley current decides the turn-on of the high side:

TI's board runs forced PWM: the low side stays on through the valley even when the current reverses. Below 2.74 A at 48 V the valley goes negative and the high side gains partial ZVS. Above it, every turn-on is hard and pays the output-charge and overlap losses of §8.

The ZVS is only partial, because charge and time must both suffice. Under a constant-current approximation the node must swing through the switch output charge within the dead time:

The valley never quite reaches −2.75 A (at no load −2.74 A), and the 55 nC is the total node charge at 50 V. Across the useful load range the node does not finish its swing within 20 ns. Forced PWM therefore buys partial ZVS at light load, not full ZVS.

Our loss model in §8 uses an energy condition without this time limit, so it treats the light-load turn-on as softer than it is. Never call a transition ZVS before checking current direction, charge and time. A published buck example optimizes exactly this negative current: Tang et al., Optimization of Minimum Negative Current BCM Synchronous Buck Converter.

TI chose, TI measured. TI chose the LMG2100R044 and the LM5148 with its adaptive dead time $t_{\mathrm{DEAD}}$, 20 ns typical (SNVSC01 §7.5). TI does not publish the dead time measured on the board. We keep forced PWM and 20 ns to reproduce TI's measured design. The negative light-load current helps commutation but costs circulating-current loss. Diode emulation avoids the reversal, but it changes the mode and the response (§10.2). Neither choice guarantees ZVS.

7. Closing the loop

7.1 The LM5148 loop with TI's parts

The LM5148 runs peak current mode. Each cycle it compares the sensed inductor current with the error-amplifier output and ends the on-time when they meet. The controller senses the current across R7 ∥ R10 = 1.714 mΩ and amplifies it by $G_{CS}$ = 10 (SNVSC01). An internal slope ramp keeps the current loop stable at any duty.

The board uses the fixed 12 V mode, so the feedback gain is $V_{\mathrm{REF}}/V_o$ = 0.8 V/12 V with no external divider. The compensation is type II on EXTCOMP: R23 = 6.8 kΩ in series with C57 = 6.8 nF, and C56 = 220 pF in parallel (TI parts, TIDMDL2). An amplifier of $g_m$ = 1.2 mS (SNVSC01) drives it.

In current mode the inductor behaves as a controlled current source at low frequency. The power stage then shows one pole, formed by the load and the output bank, and the ESR zero of §4.4. It also shows a double pole at $f_s/2$, which the slope ramp damps.

With our ramp of 84 mV/µs (ours, derived from SNVSC01 Eq. 9), the ramp ratio is $m_c$ = 1.64. That double pole then has $Q$ = 0.436 and is well damped. We use Ridley's current-mode model with TI's compensation, untuned (ti-pmp31349/scripts/loop_design.py).

At 48 V and 20 A our model crosses at 21.8 kHz with 100.8° of phase margin (ours) and 13.7 dB of gain margin.

7.2 Model against measurement: an input limit

TI measured the loop at a 10 A load (TIDT427A figs. 2-6 to 2-8). At that load:

The model crosses about 1.5 times higher and with 27–30° more phase. The cause is an input, not Ridley's model. We gave the model the polymer ESR at its maximum rating, 65 mΩ per part, which puts the ESR zero at 16.3 kHz, right at crossover.

That zero adds phase lead and lifts the mid-band gain onto a flat ESR shelf. At TI's 15.27 kHz the model's $|T|$ is only +1.9 dB, so a small gain change moves $f_c$ far. The table sweeps only the polymer ESR at 48 V and 10 A (loop-checks.json, esr_sensitivity):

TI measured 15.27 kHz / 72.8°. A lower polymer ESR brings both predicted quantities close to these measurements. Now check competing explanations. The R13/C54 sense filter adds −3.1°. A 100 ns delay adds −0.8°.

Set $g_m$ to its 1020 µS minimum and $G_{CS}$ to its 10.8 maximum. The crossover moves to 14.85 kHz, but the phase margin remains 97.3°. Gain tolerance can explain the crossover shift without explaining the measured phase.

Decision. Of these comparisons, lower ESR explains both changes. This does not measure the board's ESR. We keep the untuned 65 mΩ rating in the base model and record its limitation. Check uncertain inputs before adjusting a model to match a curve.

7.3 The load step, and the price of a lower crossover

On the 10 → 20 A step at 48 V the averaged model drops 233 mV (ours) and recovers within about 90 µs. TI measured −276 mV (TIDT427A fig. 3-7, scope minimum including switching ripple and noise). Both sit inside our 360 mV. The model is optimistic because it crosses higher than the board.

Our 35 kHz target sized the bank at 126.3 µF with (4.2a). TI crossed at ≈15.3 kHz, and its schematic notes "fcc ~15 kHz" as the design intent. At that crossover the same estimate asks for 290 µF. Our 126.3 µF would drop ≈825 mV and fail the 360 mV limit. TI's 340 µF gives ≈307 mV by the same estimate.

TI pairs a lower crossover with more capacitance. Our 126.3 µF holds only if the loop really reaches 35 kHz. With the type II network R23, C57, C56, TI measured about 15 kHz crossover at every input voltage. The phase margin was 67–73° and the gain margin 17–19 dB. We keep TI's compensation with its larger bank. A smaller bank or a higher crossover is a new design target: redesign the compensation and verify the load step again.

8. Losses, efficiency and temperature

8.1 Where the losses come from: the datasheet estimate

The ideal buck of §2.3 is lossless. The losses come from the components, not from the conversion principle. We first estimate every loss from datasheets only: LMG2100R044 (SNOSDF9B), LM5148 (SNVSC01) and Würth 74439370047, with no measured number (ti-pmp31349/scripts/loss_estimate.py). At 48 V and 20 A (ours):

There is no reverse-recovery row: the GaN half-bridge has no body diode (§6.1). The model does not include skin and proximity effects separately. These effects raise the AC resistance of the winding (recap §2.7).

Our datasheet estimate gives 96.83 % at 48 V and 20 A (ours). TI measured 95.5 %.

8.2 The losses change the duty

Replace each switch and winding by its resistance. Replace the input filter by its resistance $r_{\mathrm{in}}$ and the dead time by its drop. Keep the current in each output-side drop at $I_o$. Then apply volt-second balance again:

Here $I_{\mathrm{in}}\,r_{\mathrm{in}}$ is the drop of the mean input current across the input filter, so the switch node sees slightly less than $V_{\mathrm{in}}$. With TI's parts at 48 V and 20 A, this equation asks for $D$ = 0.2565 against the ideal 0.250 (ours, datasheet values only, loss-estimate-checks.json). The controller adds duty to cover the drops.

This is a CCM average model. If its valley goes below zero with diode emulation, or it predicts a negative output, its assumptions have failed. Its result is then not a prediction (§10.2).

8.3 The estimate against TI's measurement

TI's data have 147 rows, three of them at 0 A. Against the 144 measured points with nonzero load, the datasheet estimate errs by 2.65 pp (percentage points) rms (ours vs TI). It is optimistic everywhere, and most at light load, by up to 14.2 pp at 60 V and 0.5 A, where the fixed losses dominate.

Our curves have a kink between 2 A and 2.5 A at 48 V and 60 V, and between 1.5 A and 2 A at 30 V. There the model's high-side turn-on becomes hard (§6.2).

8.4 Calibration: what the measurement says we missed

We now fit the six loss coefficients to TI's measurement (ti-pmp31349/scripts/reverse_engineer.py). The fit reproduces TI's curve to 0.33 pp rms by construction. What it teaches is which of our estimates were low:

The core-loss gap is mainly our method's bias, not a measurement surprise. Würth publishes no core-loss data for this part. Our $k$ therefore comes from the impedance-curve peak, $R_p$ = 4.28 kΩ at 16.4 MHz, which we take as frequency independent. Steinmetz scaling makes the loss per volt² rise toward lower frequency. The extrapolation from 16 MHz to 350 kHz therefore biases our core loss low by roughly an order of magnitude.

Our 0.11 W is a lower bound. A REDEXPERT core-loss figure at 350 kHz would replace it.

With the fitted terms the model gives 95.62 % at 48 V and 20 A (ours, calibrated to TI) against TI's measured 95.5 %. Never present the fitted curve as a prediction: it agrees with TI because we fitted it to TI.

8.5 Junction temperature

$R_{\theta JA}$ = 29 K/W is the datasheet value on a JEDEC board (SNOSDF9B Table 5.4). The GaN loss of 1.58 W is our datasheet estimate. TI measured 85 °C at the same operating point, without heat sink (TIDT427A §2.3.1, fig. 2-3). That is the thermal-camera hot spot on the board bottom under the GaN IC. It is a PCB surface temperature, not $T_j$, and TI gives no ambient temperature.

The reading is therefore a lower bound on $T_j$. Our junction estimate lies 14 K below a surface that cannot be hotter than the junction. No! Our estimate is optimistic three times over. The JEDEC $R_{\theta JA}$ is not this board, the 25 °C ambient is our assumption, and the datasheet losses are low (§8.3). Always compare like with like: a thermal-camera reading is a surface temperature.

Other TI temperatures. At 10 A without a heat sink, the GaN thermal-pad vias reached 81 °C and the inductor 76 °C. At 20 A with a heat sink, TI measured 95 °C on the inductor, 92 °C on the vias and 76 °C on the heat sink (TIDT427A §2.3).

What would we improve first? At full load, investigate inductor DCR and low-side conduction, two of the largest datasheet loss terms. A lower-resistance candidate may help, but its magnetic, switching and thermal costs must also pass. At light load, get better core-loss evidence first. The fit shows that a loss is missing. It does not show which replacement part reduces it. Let the intended operating range decide which investigation comes first.

9. Proof by simulation

9.1 Python waveform checks against TI's scope captures

ti-pmp31349/scripts/ripple_checks.py solves the operating point TI captured: 48 V to 12 V at 20 A, at the measured 344.9 kHz. It uses TI's parts and the losses calibrated on TI's measurement (§8.4). The model gives $D$ = 0.2565, an on-time of 0.744 µs and $\Delta I_L$ = 5.64 A (ours, calibrated to TI). It then compares the ripple equations of §4 and §5 with TI's scope captures (ripple-checks.json):

The ideal-capacitor formula misses the output ripple by almost a factor of ten. On a mixed bank the ceramic branch carries most of the ripple current, and the polymer ESR adds the triangular part. The branch impedances, not the total capacitance, therefore set the ripple.

Never size a mixed bank's ripple with the ideal-capacitor formula alone. At the input the measurement implies ≈8.8 µF effective. Our DC-bias estimate of 10.5 µF is therefore high, and the input ripple misses our 1.0 V target (§5).

The other two proofs are already on the page: the efficiency curve against TI's measured points (§8.3) and the averaged load step against TI's capture (§7.3).

9.2 PLECS models (pending)

The lecturer draws two PLECS models from ti-pmp31349/plecs/pmp31349_buck.m and its drawing guide ti-pmp31349/plecs/README.md. The lesson supplies parameters and wiring only.

• Model 1, open loop, fixed duty (drawing guide §1–9). Pending until drawn. It must reproduce $\Delta I_L$ ≈ 5.64 A, about 47 mV of output ripple and about 1.07 V of input ripple at 344.9 kHz. It must also reproduce the conduction losses of §8.1.
• Model 2, closed loop with the LM5148 current sense, slope ramp, error amplifier and TI's compensation (drawing guide §10). Pending until drawn. It must reproduce the crossover of §7.2 and the 10 → 20 A step of §7.3, 233 mV in the averaged model.

When the lecturer draws both, their results replace the word pending here. Investigate any disagreement with the Python model. Do not average it away.

Choose the model for the question. Use the averaged model for the local loop and load step. Use a switching model for ripple and commutation. The first is simpler to inspect. The second needs more detail and computation. Compare their overlapping predictions before trusting either.

10. What if? Four variations of the finished design

The base design runs in continuous conduction (CCM): the inductor current stays above zero through the cycle,

with $R = V_o/I_o$ the load at the operating point. At the boundary $I_o = \Delta I_L/2$, which for TI's 4.7 µH at 48 V is the 2.74 A of §6.2. The duty balances the volt-seconds, while the load sets the mean current. Each variation below changes one thing and states what changes in the numbers, the waveforms and the parts (variation-checks.json).

10.1 Critical (boundary) conduction

Hold the current triangle so that it just touches zero each cycle. Its peak is then twice the load, and the frequency or the inductance follows:

Keeping TI's 4.7 µH means running at 47.87 kHz (ours). The 40 A peak then lies far above the 20.9 A at which that inductor has lost 10 % of its inductance. Keeping 350 kHz needs a different 0.643 µH inductor rated for 40 A.

Either way the RMS current rises to 2/√3 of the load, and the high side now turns off at twice the load current. Critical conduction gives a high-side turn-on at zero inductor current, so the turn-on overlap loss disappears. The output charge is still hard-switched unless the current goes slightly negative (§6.2).

Critical conduction does not mean a fixed frequency. At fixed $V_{\mathrm{in}}$, $V_o$ and $L$, (10.1a) makes $f_s$ inversely proportional to $I_o$. A controller that stays on the boundary detects zero current and starts the next pulse there. Its frequency therefore moves with load and input: at half the load, twice the frequency.

Once a deliberate negative valley is added for ZVS, recalculate the current area: $I_o = I_{\mathrm{pk}}/2$ holds only for the zero-valley triangle.

When would we choose the boundary? Keep CCM for the stated board. Boundary operation at 20 A needs a 40 A peak, above its 35 A current limit. It also changes the magnetic and RMS-current requirements.

Boundary control remains a redesign option when reduced turn-on overlap justifies those costs. It needs suitable parts, protection and a controller that accommodates the frequency range. Changing the conduction mode alone is not enough.

10.2 Discontinuous conduction

With diode emulation the controller turns the low side off when the current reaches zero, instead of letting it reverse as forced PWM does. Below the boundary the current then rests at zero until the next pulse. The cycle has three intervals: high side on ($D$), low side on ($D_2$), and both off.

Which mode at 48 V and 2 A? The CCM candidate would have a valley of 2 A − 2.74 A, below zero. With diode emulation that candidate is invalid, and the converter is in DCM. With TI's forced PWM it is valid. The negative valley then circulates current that costs conduction loss but gives the partial ZVS of §6.2.

For DCM, with $M = V_o/V_{\mathrm{in}}$ and the current triangle supplying the load:

Always check $D + D_2 < 1$: here 0.855, so the zero interval exists and the DCM model applies. The triangle area checks the load: $I_{\mathrm{pk}}/2\cdot(D + D_2)$ = 2.0 A. Substituting $K = 1-D$ recovers $M = D$, so the two models meet at the boundary.

Why $M$ no longer equals $D$. The third interval puts zero volts across L, and the length of the low-side interval depends on $V_o$. The duty falls from the CCM 0.250 to 0.2138. The conversion ratio for a given duty now depends on the load, and the control-to-output transfer function changes.

TI's board runs forced PWM and stays in CCM instead. With $KM^2 = D^2(1-M)$ the DCM gain is $M = 2/(1+\sqrt{1+4K/D^2})$. Appendix E gives the full derivation and a worked DCM case.

At light load. Keep forced PWM to reproduce the TI board, and accept its circulating-current cost. If light-load loss is the priority, investigate diode emulation. Compare its losses and control in DCM before choosing. The CCM calculation cannot decide the DCM case.

10.3 A different switching frequency

Keep the 30 % ripple at 60 V and resize L by (3.1a) for each $f_s$. The datasheet-only estimate at 48 V and 20 A (ours):

Halving $f_s$ to 175 kHz raises L to 9.14 µH. Our predicted efficiency rises from 96.82 % to 97.16 %. At 700 kHz, L falls to 2.29 µH and efficiency falls to 96.14 %. Output-charge, overlap, dead-time and gate-drive losses grow with frequency in this model.

The 350 kHz row uses our 4.571 µH rather than TI's 4.7 µH. This explains the small difference from §8.1's 96.83 %.

Before choosing a lower frequency, question the model. The sweep keeps the original DCR even as L changes. Its core-loss lower bound also becomes more optimistic at lower frequency. A larger inductor costs space and may have different losses. This sweep shows a trade-off. It does not establish an optimum.

Frequency choice. Keep 350 kHz for this comparison. Choose a new frequency only after you compare real magnetics, device losses and transient limits.

10.4 A different LC filter

Halve or double the 340 µF output bank. The filter's corner, characteristic impedance and resistive-load Q are

Without ESR and DCR, L and C cancel at $f_0$ and the peak $|Z_{\mathrm{out}}|$ equals the load, $R$ = 0.6 Ω at full load, for every C. It grows as the load gets lighter and R rises. Then only ESR, DCR and the control loop limit it.

$Z_0$ is what more capacitance buys: the open-loop deviation for a load step is about $\Delta I\cdot Z_0$, which the loop then reduces by the factor $1 + T$ (Part II). The ideal model here ignores ESR, ESL and DCR. With TI's polymer, the ESR of §4.4 damps the peak further.

Capacitance choice. Keep 340 µF with TI's compensation for the comparison with the measured board. The 680 µF alternative lowers $Z_0$ but adds hardware and changes the loop dynamics. It does not lower the ideal resonant peak. The 170 µF alternative saves space, but only a passing closed-loop load step can justify it. Either change needs a new compensation check, because this open-loop table does not prove the transient requirement.

11. What to retain

1. Write the specification first, and label every limit as given (TI) or chosen (ours). A missing limit is a design decision, not a free parameter.
2. Worst cases sit at the ends of the range. The inductor ripple peaks at the maximum input. The input-capacitor RMS current peaks at the duty nearest 0.5, here the minimum input.
3. The load step, not the ripple, sizes the output bank. Then check the ESR against $|Z_C|$ at crossover: a failed check moves the crossover or the bank. It does not go away.
4. Check real parts under real conditions: ceramics under DC bias, the inductor at its peak and at the current limit, the input bank against measured ripple.
5. The sign of the valley current and the dead time decide each switching edge. Name the device and the edge, and check charge and time, before calling anything ZVS.
6. A model gap points to an input first. The max-rated polymer ESR explains the loop gap. The impedance-curve core loss explains most of the loss gap.
7. Estimate from datasheets, then calibrate against measurement. The fit says what we missed, never what we predicted.

12. Training: problem-driven exercises

Start each exercise by making a prediction. Sketch the current path or waveform before calculating. Then choose a model and solve the problem. Compare the alternatives and explain which one you would use.

Try the problem before reading its solution. For every exercise, state your choice, one benefit and one cost. Compare a credible alternative and name the condition or measurement that would change your choice. Keep the operating point and requirements clear.

• T1–T4 are worked here, all seven parts included.
• E1–E5 are assigned Exercises. This lesson shows their first four parts. Their Solution, the last three parts, is held in the Enrolled companion lesson and released after the deadline.

Operating points. T4 works on PMP31349 itself, with the calibrated model of §8.4. The others need a mechanism that the finished GaN design hides: a diode buck, a deliberately saturating core, an authored filter or an authored loop. They use the simpler teaching model of Appendix E, a diode buck from 30–48 V to 24 V and 10 A at 100 kHz with 60 µH and 100 µF, or a stated variant of it.

Every Problem states its own operating point; never carry a number from one operating point to another.

E2–E5 examine the same LC network through four questions. How does it filter voltage (E2)? What output impedance does the load see (E3)? Where are its poles (E4)? What changes when feedback is added (E5)?

The filter equations impose an ideal switch-node voltage and place R across C. They require continuous conduction or a synchronous stage that permits current reversal. A diode buck in DCM needs Appendix E's three-interval model. The feedback examples describe small changes about a positive-current CCM equilibrium. Keep the load resistance R separate from the series resistance r.

The exercises go beyond the live route. Session 3 works one or two of them in class; the rest are assigned as reading.

T1 — Ripple shape: rounded, triangular or rectangular?

Problem

The scope shows the output ripple of a buck. On one board it is rounded, almost sinusoidal; on a second it is a triangle; on a third it carries a step at every switching edge. If the waveform becomes more angular, which part of the output capacitor is responsible, and how would you prove it? Start with the simplest current waveform and find the contribution of each parasitic on its own.

Operating point. A prescribed capacitor current: the 2 A peak-to-peak, zero-mean triangle of the teaching model at 48 V input and 100 kHz, into $C$ = 100 µF with series resistance $r_C$ (ESR) and series inductance $l_C$ (ESL). The current is imposed; the converter around it is not solved.

Why we do it

The shape of the ripple is the first clue the scope gives about which impedance dominates. Read it right and you know whether to add capacitance, lower the ESR or shorten the current loop. Read it wrong and you buy the wrong part. The same ESR also moves the loop (§4.4, §7.2), so a misread parasitic costs twice.

What matters

Model the output-capacitor branch as an ideal capacitance $C$ with series $r_C$ and $l_C$. For branch current $i_C$, with a consistent passive voltage reference:

• The three terms do three different operations on the same current: integrate, multiply, differentiate.
• Their extremes need not occur at the same instant. Adding peak-to-peak magnitudes gives a bound, not the ripple.
• A measured edge spike can also contain ringing, coupling and probe-loop pickup, so the shape alone does not uniquely identify a component.

Where it appears in practice

• PMP31349's output bank (§4.4). The polymer ESR sets the bank impedance at the loop crossover, while the ceramics carry most of the ripple current near $f_s$. TI's scope capture of the output ripple (§9.1) is the measured shape to read.
• Point-of-load (POL) regulators for processors and FPGAs. An all-ceramic bank has little ESR, so the ESL of the parts, pads and vias shows up as steps at the edges.
• Choosing between polymer, electrolytic and ceramic banks. The shape says which term to buy down first.

Possible solutions

Solution A — superpose the three terms in the time domain. For the ideal CCM buck with approximately constant load current, $i_C$ is a continuous, zero-mean triangle. Its three voltage contributions have different shapes:

Increasing the ESR alone therefore moves this ordinary buck's output ripple toward a triangle; it does not generate a square wave. A rectangular contribution points to a different current waveform or to the derivative term. E1 asks which inductor model provides exactly such an additional current component.

Prescribe the 2 A peak-to-peak triangle at 100 kHz into $C$ = 100 µF and vary only the capacitor parameters, so the comparison isolates their voltage contributions:

Why 25 mV + 20 mV does not equal 45 mV here: the capacitive and ESR extremes occur at different instants. Adding their peak-to-peak magnitudes is a conservative bound; summing their instantaneous waveforms gives the actual result. At high ESR, the triangle dominates.

The current slopes of this symmetric triangle are ±0.4 A/µs. An illustrative 50 nH of effective series inductance adds ±20 mV, a 40 mV peak-to-peak rectangular contribution. This ESL value is an intentionally visible capacitor-plus-connection example, not a selected capacitor's specification.

Solution B — read the branch impedance against frequency. In a simple model the ESR adds a zero at $1/(2\pi r_C C)$ to the capacitor branch; the ESL adds a series resonance above it. Whichever term dominates $|Z|$ at $f_s$ and its first harmonics sets the shape: the capacitive slope gives the rounded wave, the flat ESR shelf the triangle, the inductive rise the steps.

This is the view §4.4 uses for TI's bank, and it shows at once that the same ESR zero also changes the loop phase (§7.2).

Solution C — change one thing, in the model or on the bench. Set the ESL to zero and sweep the ESR. Then restore a fixed ESR and vary only the ESL. On hardware, swap one capacitor type at a time and probe at the capacitor terminals with the shortest ground connection available.

Analog Devices' Input and Output Noise in Buck Converters Explained separates the capacitive, ESR and high-frequency parasitic contributions this way.

Pros and cons

Conclusion

Use time-domain superposition first to explain the shape. It separates capacitance, ESR and ESL with little calculation, but assumes a prescribed capacitor current. Use the impedance view when the frequency range matters, and a switching model when that current assumption fails.

For the 100 mΩ case, investigate ESR before buying more capacitance: its triangular contribution dominates. For an edge step, first repeat the measurement with a short probe return. Then change one suspected element. A terminal-current jump is another explanation, examined in E1.

Our next action follows the observed shape. We do not select a replacement capacitor until a change-one-thing check supports the cause.

T2 — Is a CCM buck a current source?

Problem

An LED string or a battery needs a set mean current, not a set voltage. A designer proposes the teaching-model buck at a fixed duty and argues that its inductor already makes the current smooth. Does a fixed-duty CCM buck regulate current? If not, how would you deliver a commanded mean current, and what does each way cost?

Operating point. Teaching model, diode buck: $V_{\mathrm{in}}$ = 48 V, $L$ = 60 µH, $f_s$ = 100 kHz. Fixed duty $D$ = 0.5 into a 2.4 Ω or 4.8 Ω resistor, or into a stiff voltage such as an LED string or a battery. For the peak-controlled routes: a commanded peak of 1 A, with the load voltage between 12 V and 36 V.

Why we do it

Smooth current and regulated current are different requirements. An inductor makes current continuous on a short timescale; a current source must hold its mean delivered current close to a setpoint as the load voltage changes. Mixing up the two is a common design error, and it hides until the load voltage moves.

What matters

The duty sets a voltage. At fixed duty, the ideal CCM steady-state relations are:

At $D$ = 0.5 a 2.4 Ω load takes 10 A and a 4.8 Ω load takes 5 A, and both stay in CCM with 60 µH. The duty sets a voltage, not a current independent of the load.

A stiff load has no preferred current. A battery or an LED string imposes a fairly stiff voltage instead of behaving as a resistor. For the ideal averaged inductor:

If the imposed output voltage equals $DV_{\mathrm{in}}$ exactly, any initial mean current is an equilibrium of this simplified model: there is no preferred setpoint. A small mismatch makes the current drift instead of restoring it. At 48 V, an absolute duty error of 0.01 gives a 0.48 V average error across L, an initial slew of 8 A/ms with 60 µH, before load dynamics or resistance restore balance.

Compliance. The requested current must lie within the available output-voltage range and the component ratings. An open load cannot absorb a programmed current, so the controller needs a voltage ceiling. These limits define the compliance range.

Where it appears in practice

• LED drivers. The forward voltage of a string is stiff and moves with temperature, so the driver regulates current; many use peak or boundary control.
• Battery chargers in constant-current, then constant-voltage operation. TI's CC/CV buck discussion gives an implemented current-feedback example.
• PMP31349 itself. The LM5148 runs peak current mode (§7.1) as an inner loop under the voltage loop. Its peak control shapes the power stage; it does not hold the mean current at a setpoint.
• Laser-diode, plating and electrolyser supplies, where the process is set by current, not by voltage.

Possible solutions

Solution A — let the passive stage do it: more inductance, or the series resistance. Double $L$ while keeping $V_{\mathrm{in}}$, $D$ and $R$ fixed in ideal CCM: the ripple halves, and the settled mean current remains $DV_{\mathrm{in}}/R$. Inductance changes ripple and dynamics, not the ideal fixed-duty DC current; a larger L only slows the drift above. With series resistance and a diode drop, an approximate CCM relation is:

The resistance does set a current, but poorly. At fixed $D$, a 0.2 V change of the imposed output voltage moves the current by about 1 A if the effective series resistance is 0.2 Ω. Lower resistance improves efficiency and makes this open-loop current sensitivity larger, and temperature moves the winding resistance, the MOSFET resistance and the diode drop.

The right-hand plot of the DCM example in Appendix E shows these local slopes; negative-current extrapolations need a bidirectional stage and lie outside the diode-buck CCM domain.

Appendix E.8 gives a complete fixed-duty comparison. It changes inductance through CCM, the zero-current boundary and DCM, with independent charge and power checks. Appendix E.9 applies this reasoning to an inverter's neutral leg and compares alternative control approaches.

Solution B — an average-current loop in CCM. Sense the current, compare it with a reference and adjust the duty so that the mean current error is driven toward zero. A current-regulated CCM buck is entirely practical; a battery charger or LED driver uses this principle within its voltage and duty limits.

The difficulty of Solution A concerns operation with a fixed duty or with voltage regulation only, not a fundamental inability of CCM to act as a controlled current source. Peak control is not automatically average-current regulation. In CCM, approximately $I_o = I_{\mathrm{pk}} - \Delta I_L/2$.

If the ripple changes with the input or output voltage, a constant peak limit lets the mean current move. Average-current accuracy needs the appropriate sensing and loop objective; a peak-current ceiling by itself is a protection limit. A current-mode controller inside a voltage regulator can use peak current to regulate its power stage while the outer loop still regulates voltage.

Solution C — peak control in boundary mode. In ideal boundary operation with peak-current control, each pulse starts at zero, rises to the commanded peak and returns to zero just as the next pulse begins. The current has no inherited valley to determine, and its area gives:

This assumes approximately constant voltages during a cycle, linear ramps, no extra zero-current interval and no negative-current commutation area. The rising and falling ramps need not last equally long. For a buck with $0 < V_o < V_{\mathrm{in}}$:

With $V_{\mathrm{in}}$ = 48 V, $L$ = 60 µH and a commanded 1 A peak: at $V_o$ = 24 V, $t_{\mathrm{on}} = t_d$ = 2.5 µs, the switching frequency is 200 kHz and the mean current 0.5 A. If the imposed output voltage falls to 12 V, $t_{\mathrm{on}}$ becomes 1.667 µs and $t_d$ 5 µs; the frequency falls to 150 kHz, but the mean current stays 0.5 A.

At 36 V the ramp durations exchange and the mean current is again 0.5 A. A controlled 1 A peak delivers a 0.5 A mean, and the load decides the voltage: a 24 Ω resistor settles at 12 V, a 48 Ω resistor at 24 V.

An open circuit, or a load needing $V_o \geq V_{\mathrm{in}}$, lies outside this compliance range.

The current is not set by inductance alone. With fixed ON time, L and the applied voltage set the peak. With a fixed peak threshold, changing L mainly changes the time to reach that peak, and so the frequency. The control law is part of the current-source behaviour.

This is a useful current-regulation architecture: the controller sets a peak and detects the zero-current boundary, while the load determines the voltage required to accept that current. Sensor error, propagation delay, nonlinear inductance and additional commutation intervals introduce practical current error.

Solution D — pulse charge in DCM. In DCM the same current triangle is followed by a zero-current interval. Its occupied fraction of the period is:

The delivered charge per cycle and the mean current are:

Why the denominator matters: $I_{\mathrm{pk}}/2$ is the mean during the triangle, not over a full DCM period. At $V_o$ = 24 V and a 1 A peak the triangle lasts 5 µs and delivers 2.5 µC. Repeated every 5 µs it gives boundary operation and 0.5 A; repeated every 10 µs it gives DCM, $\rho$ = 0.5 and $I_o$ = 0.25 A. The repetition rate sets the mean.

Peak control alone is not enough at a fixed DCM frequency. Keep the 1 A peak and 100 kHz repetition rate. At $V_o$ = 12 V or 36 V, the triangle lasts 6.667 µs and gives 0.3333 A mean. At 24 V, the mean is 0.25 A. The DCM mean therefore still depends on $V_o$:

At $D$ = 0.15 this gives 0.135 A at 19.2 V and 0.060 A at 28.8 V, both in DCM. To hold the current, control the pulse area or the repetition rate, compensate for the conducting fraction, or close an average-current loop; feedforward can estimate the duty while feedback corrects losses and uncertainty.

Every such calculation needs a physically valid $\rho < 1$. This pulse-charge view explains why DCM and boundary operation can be especially convenient for current delivery: resetting the inductor current removes one inter-cycle initial-current uncertainty. It does not remove output-capacitor state, load compatibility or the need to define a controller.

DCM is not an ideal current source either, and the two-state CCM transfer functions of E2–E5 must not be carried unchanged into DCM or variable-frequency boundary operation.

Pros and cons

For the ideal triangles of C and D, the inductor RMS current is $I_{\mathrm{pk}}\sqrt{\rho/3}$ against a mean of $I_{\mathrm{pk}}\rho/2$. Easier pulse-current control and favourable commutation have a conduction-loss cost.

Conclusion

A fixed-duty CCM buck does not set a preferred current. More inductance slows a current change but does not regulate its mean.

For accurate mean current at fixed frequency, choose the average-current loop. It needs sensing and compensation, but keeps ripple and RMS current low. A peak ceiling alone is not an equivalent regulator.

Boundary peak control is a valid alternative when variable frequency and higher RMS current are acceptable. Here it delivers half the peak current in the ideal model. Choose fixed-frequency DCM only with pulse-area or repetition-rate control, or feedback that corrects the mean.

For a charger requiring accurate current, keep the average-current loop as the design route. For a driver prioritising simple boundary operation, investigate the peak-controlled alternative. State the compliance range and current-error budget before selecting hardware.

T3 — Saturation: is the peak current safe?

Problem

An inductor passes the steady-state ripple and RMS checks, and the voltage loop is stable at every operating point. Can a load step or an input step still drive the inductor into saturation? If so, what would you add to keep the peak current safe, and what does it cost?

Operating point. Teaching model, a buck whose freewheeling path carries positive current only (diode emulation), regulated to 24 V at about 8 A, $f_s$ = 100 kHz, $C$ = 100 µF, winding resistance 50 mΩ. Disturbances: a load step from 3 Ω to 2 Ω at $V_{\mathrm{in}}$ = 48 V, and an input step from 30 V to 48 V at $R$ = 3 Ω.

Authored magnetic curve: 60 µH up to 14 A, falling linearly to 6 µH at 18 A, and 6 µH above that, with no hysteresis, thermal dependence or core loss. A real Isat rating normally describes a specified percentage inductance drop, rather than an abrupt universal failure current; use the manufacturer's bias and temperature information.

The sampled voltage controller sees only the output voltage:

with $K_p$ = 0.03 duty/V and $K_i$ = 100 duty/(V·s), one duty update per period, and the integrator frozen when it would push the duty further beyond a bound. This simple anti-windup acts at those bounds; it does not track the separate current-limit override. Its local linear sampled model has all poles inside the unit circle at the three nominal conditions, so local voltage-loop instability is not required to produce a current excursion.

This is an intentionally weakly damped teaching loop, not an optimised regulator or a model of a particular IC.

Why we do it

Voltage regulation commands energy delivery in response to the output error. By itself it imposes no instantaneous ceiling on the current in the inductor or the switch. The steady-state checks are the easy ones; the transient peak decides whether the part survives. This is a limitation of an unprotected voltage-only control path, not a rule that every voltage-mode regulator lacks protection.

A voltage-mode controller may include a separate fast current comparator, overload timer and shutdown logic; the PWM regulation architecture and its fault protections must be assessed separately.

What matters

Flux linkage accumulates over cycles. Do not impose the steady-state conversion ratio on every cycle:

For linear L this flux-linkage change is L times the current change. In periodic steady state the integral is zero. During a transient it can be positive for several consecutive periods, moving the current and the flux to a higher operating point. That is how the converter meets a new load; a nonzero cycle integral is not automatically a fault.

• CCM does not require the current to return to zero, only to its previous-cycle value once periodic operation is re-established. The concern is whether the transient peak exceeds the magnetic and semiconductor limits before the controller restores balance. Saturation can also exist in an undesirable periodic waveform: zero net volt-seconds alone does not prove that the core stayed out of saturation within the cycle.
• Load step: inductor current cannot jump, so the capacitor supplies the deficit and $V_o$ falls. The controller lengthens the ON time to restore $V_o$ and recharge $C$; the inductor must supply both the new load and the recharge current, so its transient peak can exceed the final load current plus half the ripple.
• Input step: if $V_{\mathrm{in}}$ rises before the duty falls, each existing ON pulse applies more voltage to L. As a frozen-state estimate, at 8 A and 24 V from 30 V with 50 mΩ, $D$ ≈ 0.81333; raising the input to 48 V adds about 14.64 V to the cycle-average inductor voltage. At 100 kHz that is 146.4 µV·s per cycle, an initial 2.44 A rise per cycle with 60 µH, until $V_o$, current and duty respond.

Saturation steepens the ramp. For a nonlinear but memoryless magnetic characteristic, define the differential inductance:

As the core approaches saturation, $L_{\mathrm{diff}}$ falls, and the same 24 V across L rises at 0.4 A/µs with 60 µH but 4 A/µs with 6 µH. A controller still requesting ON time can therefore underestimate the peak severely if its design assumes constant L.

Do not use $v = d[L(i)i]/dt$ with a datasheet differential-inductance curve as though $L(i)i$ were the flux linkage: integrate the curve to obtain $\lambda(i)$, and use $\lambda$ as the magnetic state.

Where it appears in practice

• PMP31349 (§3.3). TI sets the peak current limit at 35 A, while the Würth inductor has lost 10 % of its inductance at 20.9 A. In an overload the inductor runs far past that point: always check the inductor at the current limit, not only at full load.
• Start-up into a large capacitive load, where the inrush current, not the load, sets the peak.
• 48 V battery buses and other supplies with line transients, where an input step is part of the specification.
• Voltage-mode controllers with a separate fast current comparator: TI discusses such controllers in its voltage-mode/current-mode comparison.

Possible solutions

Each solution is compared with the same voltage controller and the same disturbances. Peaks and energy checks use a 2 ms simulation with the disturbance at 0.2 ms (scripts/saturation_transient_example.py):

For the load step the final load current is about 12 A, below the 14 A knee, yet the unprotected transient crosses the knee into the 6 µH region. The input step is worse: the nonlinear curve more than doubles the peak that a constant-60-µH calculation predicts.

Solution A — a bigger core. Keep the controller and choose an inductor that stays linear past the largest transient peak: the linear column says above 21.58 A in this example, plus margin for tolerance and temperature. No new circuit is needed, and the loop sees the inductance it was designed for.

Solution B — a separate fast peak-current comparator. Keep the existing inductor and voltage loop. Add a comparator with a 13 A trip, below the saturation knee. Allow an illustrative 200 ns propagation delay. After a trip, hold the switch off for the rest of the period.

If current remains at or above the threshold at the next cycle start, skip that ON pulse. The simulated peaks are 13.083 A and 13.076 A. They exceed 13 A because current keeps rising during the comparator and gate-drive delay:

With about 24 V, 60 µH and 200 ns the extra rise is about 80 mA, consistent with the protected traces. If the comparator acted only after $L_{\mathrm{diff}}$ had fallen to 6 µH, the same voltage and delay would add about 0.8 A. With zero delay the trip caps the current at 13 A, which makes the delay overshoot directly measurable.

The figure shows the first 550 µs after each event, a transient window, not a claim that every trace has settled. The output-voltage and delivered-duty panels show the price of limiting current: in the input step even the protected model reaches about 30.02 V at its output. Limiting the current below the knee does not by itself prevent an output overvoltage.

Solution C — shape the disturbance instead of clipping it. Input-voltage feedforward cuts the duty disturbance of a line step. Appropriate voltage compensation, soft start, anti-windup and enough transient energy storage reduce unnecessary excursions. Sustained overload may need longer OFF intervals, foldback, hiccup or shutdown. None of these sets a hard instantaneous ceiling.

Solution D — peak-current-mode control. Make the current comparator the PWM itself: every ON pulse ends when the sensed current reaches the command, and a clamp on the command is a cycle-by-cycle limit. This is how the LM5148 runs PMP31349 (§7.1). The sensing, blanking and timing constraints of B remain.

Pros and cons

Conclusion

Keep the separate fast peak comparator for this transient problem. A stable voltage loop does not enforce the magnetic limit. The 13 A trip keeps the demonstrated peaks below the 14 A knee, while the delay explains why they exceed 13 A.

A larger core is an alternative when the required normal transient needs more current. It costs magnetic hardware and still needs an overload check. Better damping can reduce excursions, but does not impose a hard ceiling.

Retain the trip and improve the transient response if necessary. If it interrupts a required load step, reconsider the core and threshold together. Include sensing error, delay, tolerance and temperature before treating that threshold as a hardware setting.

The model predicts electrical stress, not component failure. A slower average-current limit can miss a peak inside one pulse.

Change one thing: replace the saturable element by constant 60 µH, then restore it and add only the peak trip. Finally set comparator delay to zero. Each comparison isolates one cause.

Coilcraft explains the link between saturation and increased current slope. Analog Devices' AN-149 discusses voltage and current control and transient limiting.

T4 — Which parameter is worth improving? Sensitivity of PMP31349

Problem

A colleague has budget to improve one thing on PMP31349, to raise its efficiency and tighten its open-loop output: a lower-DCR inductor, a lower-resistance GaN stage, a faster switching edge, a larger inductance or a higher switching frequency. Which parameter matters most, and does the ranking still hold at light load? Rank the parameters at two operating points and say what your ranking depends on.

Operating point. PMP31349 at $V_{\mathrm{in}}$ = 48 V and $V_o$ = 12 V, $f_s$ = 350 kHz (TI), at $I_o$ = 20 A and at 5 A. The model is the calibrated loss model of §8.4: our datasheet parameters plus the terms fitted to TI's measurement (ti-pmp31349/scripts/sensitivity.py, sensitivity-checks.json).

Each parameter is raised by 10 % on its own. Every number in T4 comes from that file; the base efficiencies are ours, calibrated to TI, and the sensitivities are results of our calibrated model, not measurements.

Why we do it

A sweep shows how a model changes across a range; a local sensitivity is the slope at one specific point. A ranking without its operating point ranks nothing: the part that wins at full load can lose at light load. And the money for a better part is spent once, while the converter runs at every point of its range.

What matters

• State what is fixed before differentiating. Two views answer different questions. Open loop: $V_{\mathrm{in}}$, the duty $D$ and the load current are held, and $V_o$ moves. Regulated: the loop holds $V_o$ = 12 V, the duty moves, and the cost shows as efficiency.
• Know which terms are fitted. The overlap time, the core-loss factor, the output-charge factor and the resistance rise with load are fitted to TI's measurement (§8.4). Their sensitivities say what the fit contains.

A local sensitivity is a tangent. The prediction for several small changes is

not a guarantee for a large change. Recompute the operating point when a change is large or crosses a mode boundary, such as the high side's change to hard turn-on (§8.3) or the CCM boundary (§10).

Absolute or normalised. An absolute sensitivity has units, such as V/Ω. A normalised sensitivity compares fractional changes:

Raising every parameter by 10 % is a normalised comparison. A specified change, such as "10 mΩ less", needs the absolute slope. Normalisation misleads near a zero nominal value.

Where it appears in practice

• Choosing between two inductors or two GaN stages for a 48 V to 12 V intermediate-bus or battery-bus converter such as PMP31349.
• Cost-down reviews: which specification can be relaxed without losing efficiency where the product actually runs.
• Tolerance and worst-case analysis: the open-loop output shift and the duty headroom over production spread and temperature.
• Light-load efficiency claims in a datasheet, where the ranking differs from full load.

Possible solutions

Solution A — analytic derivatives of the averaged equation, open loop. Start from the loss-corrected volt-second balance of §8.2:

Here $r_{sh}$ is the current shunt ($r_s$ in §8.2; in T3 and E1 $r_s$ is a winding resistance). Hold $V_{\mathrm{in}}$, $I_{\mathrm{in}}$, $D$ and $I_o$ and differentiate:

Why: the winding and the shunt carry the current for the whole cycle, the high side only during $D$, the low side during $1-D$, and the dead-time drop grows with every switching edge. At $D$ = 0.2565 (20 A) the low side conducts for almost three quarters of the period.

Both sides are the same LMG2100R044 resistance in the model, so the ratio of their effects is $D/(1-D)$: +10 % gives −3.16 mV on the high side and −9.16 mV on the low side. This is the synchronous form of the diode-buck rule that a diode drop is especially visible at low duty (Appendix D): the low side has taken the diode's place.

The winding gives −10.0 mV at 20 A and −2.50 mV at 5 A, a ratio of four, as $\partial V_o/\partial r_L = -I_o$ predicts. The dead-time drop hardly depends on the load: +10 % $f_s$ costs −2.10 mV at 20 A and −2.08 mV at 5 A.

Solution B — perturb the full loss model, one parameter at a time, regulated. Hold $V_o$ = 12 V. Increase one parameter by 10 % and solve the operating point again. Retain ripple, partial high-side ZVS, fitted overlap and fitted core loss.

The calibrated base point at 20 A is 95.62 %, with $D$ = 0.2565. At 5 A it is 95.66 %, with $D$ = 0.2519. The table gives the efficiency change in percentage points. It also gives the fixed-duty output-voltage change at 20 A for comparison with Solution A.

At 20 A, conduction and fitted overlap dominate. A 10 % parameter change affects efficiency by about 0.07–0.08 pp. At 5 A, the fitted core term dominates. Increasing $L$ by 10 % gains 0.327 pp because ripple falls. The fitted core loss scales with $\Delta I_L^{2.2}$.

The frequency result needs caution. Increasing $f_s$ by 10 % gives +0.177 pp at light load in this model. The sign of the hardware improvement is not established.

At fixed $L$, increasing $f_s$ reduces flux swing: $\Delta B \propto 1/f_s$. Steinmetz gives $P \propto f^{\alpha}\cdot\Delta B^{\beta} \propto f^{\alpha-\beta}$. Our fitted term omits the $f^{\alpha}$ factor. It therefore credits a saving near $f^{-2.2}$, rather than $f^{-(\beta-\alpha)}$. The actual core-loss saving may be much smaller. It may erase the predicted +0.177 pp net gain.

Decision. Use the ranking to choose what to investigate. Check the magnetic-loss model before changing frequency. §10.3 shows the same limitation. A sensitivity calculation describes the model we supplied.

The regulated view also says what the loop must supply. With equal high- and low-side resistance the duty of §8.2 is $D \approx [V_o + I_o(r_L + r_{sh} + R_{LS}) + 2t_d f_s V_{SD}]/V_{\mathrm{in}}$, so $\partial D/\partial r_L \approx I_o/V_{\mathrm{in}}$. The loop absorbs the open-loop shift of Solution A by adding duty, while efficiency and temperature still deteriorate.

Regulation hides the output-voltage sensitivity, not the loss; near the maximum duty a small added drop can leave the controller without headroom.

Solution C — a global sweep over the operating range. Recompute every point of the map, for example TI's 147-row efficiency grid of §8.3, instead of a tangent at two points. A sweep catches the mode boundaries that a slope cannot see: the high side's change to hard turn-on, the kink of §8.3, and the DCM edge of §10.2.

A continuous-looking surface beyond a mode boundary can be mathematically smooth and physically wrong. The ntbees2 Pareto study over $f_s$ and $L$ (ti-pmp31349/figures/04_pareto_fs_L.svg) is such a sweep; it predates the parameter alignment and is cited as a side study only.

Pros and cons

Conclusion

At 20 A, investigate conduction resistance and switching overlap first. At 5 A, obtain better magnetic-loss evidence before changing a part: the ranking is dominated by a fitted core term.

Use the simple derivative to explain a mechanism. Use the regulated perturbation model to rank its local efficiency effect. A wider sweep is preferable when the change approaches a conduction-mode boundary, but needs more computation and careful interpretation.

For the proposed light-load frequency change, keep the hardware unchanged until the core model is improved. Its predicted benefit is not established by the fitted ripple term. At full load, compare actual resistance and switching candidates using the relevant losses.

Report the operating point, held quantities, regulated or fixed duty, and model limits. Keep percentage changes separate from percentage points. Check selected points with current area, volt-second balance or power balance.

E1 — Inductor loss: a step in the terminal current

Problem

Can an inductor have a step in its terminal current? The output ripple shows a step at each switching edge. Capacitor ESL is negligible. Compare at least two inductor models.

In the drawn model, $r_s$ is in series with the parallel combination of $L$ and $R_p$. At switch turn-off, calculate the terminal-current jump, output-voltage jump and mean $R_p$ loss. Use these four cases:

• No parallel branch, with $r_C$ = 50 mΩ.
• $R_p$ = 240 Ω, with $r_C$ = 50 mΩ.
• $R_p$ = 24 Ω, with $r_C$ = 50 mΩ.
• $R_p$ = 24 Ω, with $r_C$ = 0.