Circuit and electronics foundations for power electronics

Audience: electrical engineering students refreshing earlier circuit courses.
Teaching time: two sessions of 90 minutes.
Purpose: connect circuit laws, waveforms and system models to the design of real power converters.

Use this lesson in two ways. Follow the teaching route for a refresher on circuit foundations. Later, return with a symptom and use chapter 16 to find a worked example.

Most numerical examples are teaching scenarios. Device data and published measurements are identified where used. Voltages and currents follow the passive sign convention unless stated otherwise.

The aim is to learn how an engineer approaches an unfamiliar circuit. Start with what you can observe. Make a prediction, choose a model and check the result. The equation should help you make a decision. Explain the benefit and cost of your choice. When another route is credible, say what would make you choose it.

Course organisation and assessment

The following arrangements were announced in the introductory lesson on 16 October 2026. They apply to the course as a whole, separately from the technical recap and its suggested teaching route below.

• Project and examination: choose a power-electronics kit from the course list, preferably a different kit for each student. Analyse its operation using the project checklist, calculations and simulation. Bring the project to the examination and explain its strengths, limitations and possible improvements, including what happens when a component value changes. The exercise mirrors an engineering assignment: understand an existing design well enough to evaluate and improve it. Project material was announced as available on the lecturer's GitHub; use the course-provided repository and checklist.
• Mandatory exercises: assigned exercises contribute to the evaluation and must be submitted by the next lesson. Final numerical results will be supplied for comparison; these are not complete worked derivations. Regular work throughout the course is part of the assessment. No numerical weighting between exercises and the project examination was specified in the recording.
• Books, AI and other tools: these may be used for the project and exercises. Students must understand the submitted reasoning and be able to explain and defend their calculations, models and design decisions themselves.
• Interactive lessons: interrupt when an explanation is unclear, question assumptions and point out errors. The aim is to practise engineering judgement and problem solving, with regular breaks during the teaching afternoon.
• Proposed company visit: a visit near the end of the course in January was discussed, potentially to Regatron in Arbon to see power supplies and EMC facilities. The destination and arrangements were tentative, not a confirmed booking.

Engineering approach: estimate, model, then verify

Before opening a simulator, sketch the current path. Mark the voltage references and stored energy. Estimate the expected voltage, current or time scale. Check the units.

Choose the simplest model that can answer your question. Compare its result with your estimate. If they disagree, inspect the assumptions before adding more detail. Add a parasitic or nonlinearity when it could change the decision.

A solver can print six digits without knowing the actual capacitance under bias or the winding temperature. More digits do not make uncertain inputs accurate. Use component data, vary uncertain values and compare with measurements where available.

The roughly 30% uncertainty discussed in the lesson was an example, not a general accuracy limit. Ask what the model can establish. A simple model may explain the failure even when it cannot reproduce every switching edge.

Learning outcomes and teaching route

By the end, you should be able to:

• Draw the source, load and complete current path.
• Use circuit laws and equivalent sources to explain loading.
• Sketch R/L/C waveforms and apply transformer winding conventions.
• Choose mean, RMS or instantaneous values for the calculation.
• Estimate parasitic effects and check periodic balance.
• Read impedance and Bode plots within the model's limits.
• Choose a regulation architecture and explain the trade-off.

Chapter 16 is a reference bank. The four cases named in the teaching route fit within the two sessions. Read the longer solutions afterwards. Use the remaining cases when the corresponding problem appears in a later lecture or project.

Sections 16.9–16.10 are optional advanced extensions. Their dielectric-absorption and boost-zero derivations are outside the two-session assessment core. Other extensions are marked in the example index.

1. Networks: what the source actually supplies

1.1 Voltage, current, power and reference directions

Voltage is a potential difference between two nodes. Current is the rate of charge transfer. A ground symbol selects a reference potential; it does not automatically mean protective earth, an ideal conductor, or galvanic isolation.

With current entering the positively labelled terminal, positive instantaneous power means absorption:

Kirchhoff's laws express charge continuity at a node and voltage consistency around a lumped circuit loop:

The lumped model assumes that propagation and distributed field effects can be neglected on the time and length scales of interest. At fast edges, a connection may require a transmission-line model, even when the repetition frequency is modest.

1.2 Ohm's law, dividers and loading

For an ideal linear resistor:

Resistances add in series; conductances add in parallel. For an unloaded divider:

With a load, replace $R_2$ by $R_2\parallel R_L$. Do not apply the unloaded formula to a power output with a significant load.

Worked example. A 12 V source and two 1 kΩ resistors produce 6 V without a load. Their Thévenin resistance is 500 Ω. Connecting a 1 kΩ load gives:

This is the motivation for a regulated source: the desired output should remain within tolerance as the load changes.

Divider or regulator? Keep a divider when the load is small enough for its voltage error and standing loss to be acceptable. Use a regulated source when the load range requires a stiffer output. Check both loading and dissipation before deciding.

1.3 Thévenin, Norton and superposition

A linear two-terminal network can be represented by a voltage source with series impedance or a current source with parallel impedance:

For a purely resistive circuit, use $R_{\mathrm{Th}}$. To find it, deactivate independent voltage sources by shorting them and independent current sources by opening them. Keep dependent sources active; apply a test source when needed. Apply superposition to voltages and currents in linear networks. Power must then be calculated from the resulting total waveform, since it is quadratic or bilinear.

Worked example continued. The divider of section 1.2 is, as a Norton source, 12 mA in parallel with 500 Ω. The 1 kΩ load takes 12 mA × 500/(500 + 1000) = 4 mA, that is 4 V, the same answer as before. Use the Thévenin form when the question is about voltage drop under load and the Norton form when branches share a current; a source transformation never changes what the load sees.

Converter connection: a regulated supply still has an output impedance. In a local model, a load-current perturbation causes a voltage perturbation approximately equal to minus the supply impedance times that current perturbation.

Choose the convenient equivalent. Thévenin makes voltage drop easy to see; Norton makes branch-current division easy to see. Both describe the same linear port. Change representation when it simplifies the question, retaining dependent sources and the same load.

1.4 Units, prefixes and reference levels

Keep physical units in calculations: Ω = V/A, F = A·s/V and H = V·s/A. For example, nH × A/ns gives volts directly. Remember m = 10⁻³, µ = 10⁻⁶, n = 10⁻⁹ and p = 10⁻¹²; confusing millimetres with metres changes a geometry estimate by a factor of one thousand.

Dimensional-analysis check. For the plate-capacitance estimate $C=\varepsilon_0\varepsilon_r A/d$, permittivity has units F/m, relative permittivity is dimensionless, area has units m² and separation has units m. Thus (F/m) × m²/m = F. Reversing A/d would fail this check. Also check the physical trend: larger overlap increases capacitance, while greater separation reduces it. Section 3 applies this estimate to PCB conductors.

A decibel is a logarithmic ratio, not an independent physical quantity. An absolute level needs a reference: dBV refers to 1 V, dBµV to 1 µV, and dBm to 1 mW. For the same RMS voltage, the numerical dBµV level is 120 dB above its dBV level.

Converting dBm to voltage also requires the impedance. Section 12 explains amplitude versus power ratios; never add a dBm power level to a voltage without defining the conversion.

1.5 Static resistance versus incremental resistance

An ideal positive resistor has both a positive voltage/current ratio and a positive slope. An actively regulated load can behave differently. For an approximately constant input power P, its input current is P/V: a small drop in input voltage makes it demand more current. The DC ratio V/I is still positive, but the incremental resistance is negative.

This is a local model of the controlled load, not a passive resistor delivering free energy. Section 12.5 connects this behaviour to input-filter stability and Middlebrook's impedance criterion.

2. Basic elements: R, L, C, transformer and coupled inductors

2.1 Ideal component models

The transformer is a two-port element that couples two winding circuits. Its last-column expression is the input impedance with a specified secondary termination, rather than a standalone one-port impedance like R, L or C. Section 2.4 defines its voltage/current references and practical equivalent circuit.

Finite voltage cannot change ideal inductor current instantaneously. Finite current cannot change ideal capacitor voltage instantaneously. Opening an inductive current path therefore creates a voltage until another path conducts, a parasitic capacitance charges, or breakdown occurs. Connecting an ideal voltage source directly to a capacitor at a different voltage requires an impulse of current in the ideal model.

Waveform pairs to sketch. Because $v_L=L\,di/dt$, a constant voltage across an inductor produces a linear current ramp: 12 V across 10 µH for 2 µs raises the current by $\Delta I=V\Delta t/L=2.4$ A. A square voltage therefore gives a triangular current, which is the inductor-current ripple of every PWM converter.

Dually, a constant current into a capacitor ramps its voltage: 1 A into 10 µF for 10 µs gives $\Delta V=I\Delta t/C=1$ V, and a triangular current gives a parabolic voltage, the output-capacitor ripple of a buck. Read the pairs in both directions as well: a triangular inductor current implies a square inductor voltage, and a voltage step forced onto an ideal capacitor implies an impulse of current.

The volt-second and ampere-second products in these sketches are the quantities balanced in section 7.

Real inductors have winding resistance, core loss, saturation, leakage flux and interwinding capacitance. Real capacitors have ESR, ESL, leakage, voltage dependence and finite ripple-current capability. An apparent wire is part of a current loop with resistance and inductance.

2.2 Constants as engineering scales

The familiar $4\pi\times10^{-7}$ H/m is an excellent approximation to $\mu_0$, rather than an exact SI definition today. See NIST's CODATA table. Vacuum wave impedance is not automatically the characteristic impedance of a PCB trace.

For a uniform linear medium, use $D=\varepsilon E$ and $B=\mu H$. For a simple magnetic circuit:

These connect geometry and material properties to inductance, transformer volt-seconds and eventual saturation. Relative permeability in a ferromagnetic material is generally not a fixed constant over all operating conditions.

Reluctance: the magnetic circuit's resistance. $\mathcal R$ is the reluctance, in A/Wb (ampere-turns per weber). It plays the role of resistance in a magnetic circuit: the winding's ampere-turns $Ni$ drive flux $\Phi$ through it, as voltage drives current through a resistor. Reluctances in series add, like resistors. Core data sheets give the inverse, the inductance factor $A_L=1/\mathcal R$ in nH per turn², so that $L=N^2A_L$. Inductance grows with the square of the turns: double the turns, four times the inductance.

Predict. A ferrite core has a magnetic path length $\ell_e$ = 50 mm, cross-section $A_e$ = 50 mm² and $\mu_r$ = 2000. We cut a 0.5 mm air gap into the path. Which part sets the inductance: 50 mm of ferrite or 0.5 mm of air?

The gap is 1 % of the path, yet it holds 95 % of the total reluctance. $A_L$ falls from about 2510 nH to 120 nH, so 20 turns give 1.0 mH without the gap and 47.9 µH with it. The calculation ignores fringing, which makes the real gap look slightly larger in area.

Why accept 20 times less inductance? Suppose $\mu_r$ halves with temperature or DC bias. The ungapped inductor loses 50 % of its inductance; the gapped one loses only 4.5 %. The gap also stores most of the energy and raises the current at which the core saturates. Its cost is more turns for the same inductance, hence more copper loss, and fringing flux that heats nearby winding layers. Choose an ungapped core when inductance per turn matters most and the DC current is small, as in a common-mode choke. Choose a gapped core when the inductor carries DC, as in a buck. Powder cores spread the same gap through the material.

Transformer winding voltage follows the same Faraday relation. Section 2.4 develops the ideal two-port element and adds magnetizing inductance, leakage and losses to form a practical model.

2.3 A useful first estimate: 1 µH/m for a two-wire loop

For an air-insulated pair of long, round, parallel conductors, define $d$ as the wire diameter and $D$ as the centre-to-centre spacing. The external loop inductance per unit length in the quasi-TEM model is:

For $d/D\ll1$:

Engineering rule for this recap: use 1 µH/m = 1 nH/mm as the first estimate for an ordinary two-wire loop of this order of spacing. The logarithmic geometry dependence explains why it is often useful. Air gives approximately vacuum permeability; it does not remove the geometry factor.

The expression excludes internal conductor inductance; a pair of nonmagnetic round wires with uniform low-frequency current adds approximately 0.1 µH/m internally, which diminishes as skin effect develops. MIT's electromagnetics notes provide the field and transmission-line background.

Here the length is the one-way length of the pair; the return conductor is already included. Do not double the length again. Closely spaced broad power/return planes can have much lower inductance. For wide parallel plates, ignoring fringing:

This is why the two-wire estimate is a useful classroom assumption but cannot determine actual CPU-plane layout dimensions by itself.

2.4 Transformer as a basic two-port element

What it does: a transformer transfers electrical power between winding circuits through a common magnetic field. The ideal element changes voltage, current and impedance according to its turns ratio while conserving instantaneous power. Separate primary/secondary windings allow galvanic isolation; the physical insulation construction determines the actual isolation rating. Interwinding capacitance still provides a high-frequency coupling path.

Ideal model and dot convention

Define n = N₁/N₂. Label both winding voltages from the dotted terminal to the undotted terminal, and both port currents entering their dotted terminals. Then:

The minus sign follows from the two passive port references: when the primary absorbs power, the secondary delivers it. If instead the secondary current arrow points out of its dot toward the load, the delivered-current relation is i₁ = iout/n. Reversing a winding connection reverses the corresponding voltage polarity. Dots identify relative winding polarity, not protective earth or a common electrical node.

The ideal transformer has perfect coupling, no winding resistance, no leakage and no magnetizing-current requirement. It stores no energy by itself. A pair of perfectly coupled inductors with finite inductance still has a magnetizing energy state, so it is a different model.

Reflecting a load and a worked example

With a load connected across winding 2, define the load current as leaving the secondary dotted terminal. The primary sees:

Resistance, reactance and complex impedance all reflect with n² when moved from secondary to primary. Moving an impedance from primary to secondary divides it by n². This scaling also applies to a local incremental impedance; it does not change the sign of a negative incremental resistance.

Example: an ideal 4:1 transformer is driven with a 48 V RMS sinusoid and supplies a 6 Ω secondary resistor:

The current and voltage ratios are inverse; both cannot increase while conserving power. With the signed port-current references above, the secondary current phasor is opposite to the delivered load-current phasor. The table uses current magnitudes.

From the ideal element to a practical transformer

The figure's approximate model refers the load and winding losses to the primary, so no turns-ratio element remains in that drawing:

• Magnetizing inductance Lm: requires current to establish flux, including at no load. It stores magnetic energy. For an idealized sinusoidal winding voltage, its RMS current magnitude is V/(ωLm).
• Core-loss resistance Rcore: represents average core loss approximately around the selected waveform, frequency and flux swing. A fixed resistance is not a universal model of hysteresis and eddy-current losses.
• Leakage inductance Lσ: represents flux that does not link both windings. It causes load-dependent voltage drops, switching spikes and resonances with capacitance.
• Winding resistance: produces copper loss and load-dependent voltage drop. In a primary-referred approximation, Rcu ≈ R₁ + n²R₂; leakage terms can be referred in the same way when the chosen equivalent circuit permits their combination.
• Winding and interwinding capacitance: becomes important at high frequency and across an isolation barrier; it is omitted from the simple low-frequency drawing.

For coupled-inductor descriptions, mutual inductance is M = k√(L₁L₂), with coupling coefficient between zero and one for a passive reciprocal pair. The detailed equivalent model and parameter reference side must be stated. Combining all series losses ahead of the magnetizing branch, as in the figure, is an approximation suitable when magnetizing current is small relative to referred load current.

Volt-seconds, flux reset and the limit of the ideal model

For the induced winding voltage e₁ and effective core area Ae:

For a rectangular pulse this becomes:

Example: 48 V across a 20-turn winding with 100 mm² effective core area for 5 µs changes flux density by 0.12 T. An equal negative volt-second interval brings B back to its starting value. This specifies a flux change, not its absolute peak: initial flux, DC bias and the material's usable operating range still matter.

With significant copper drop, integrate the induced/core voltage rather than treating the terminal voltage as identical to it.

A repeated nonzero net induced volt-second area causes flux to walk from cycle to cycle. Sustained DC voltage applied to a real finite-core winding ramps flux and can drive saturation; the algebraic ideal-transformer ratios alone do not expose that failure. Periodic operation needs flux reset, provided by the topology and drive waveform.

Converter connection: a forward-type stage transfers energy to the secondary during the transfer interval and must also reset magnetizing flux. A flyback deliberately stores energy in magnetizing inductance, often largely in a core gap, and releases it in another interval. Treating the flyback magnetic component as only an ideal turns-ratio element misses its main energy-storage function. MIT's magnetics notes provide the next reading step.

Which transformer model? Start with the ideal ratio for reflected load and power. It is easy to inspect but misses magnetizing current and parasitic drops. Use the practical model when those effects can change voltage stress, loss or flux margin.

2.5 Coupled inductors as a basic energy-storage element

What changes from two independent inductors: some magnetic flux produced by either winding links the other. A changing current in one winding therefore contributes to the voltage of the other. Coupling can occur through a shared magnetic core or through the surrounding field. A familiar two-winding symbol does not by itself tell us whether an ideal transformer or a finite-inductance energy-storage model is intended.

Self-inductance, mutual inductance and dots

Use the same passive references as in section 2.4: voltages from dot to undotted terminal, and both currents entering their dots. For a linear reciprocal pair with fixed parameters:

The flux linkages λ have units of weber-turn. Here M is nonnegative and winding polarity is encoded by the dots. Reversing one current reference reverses the corresponding mutual signs; do not change a sign merely because the two coils are drawn on opposite sides of a core. A rising current entering winding 1's dot induces a positive voltage at winding 2's dot under these references.

The coupling coefficient is:

k = 0 gives independent inductors. k near one gives tight coupling; k below one means imperfect flux linkage. For a passive linear pair, M² ≤ L₁L₂ ensures nonnegative stored magnetic energy. The k = 1 idealization makes the inductance matrix singular, so a model that needs its inverse must treat the associated constraint correctly.

Stored energy and the distinction from an ideal transformer

The mutual term can add or subtract, depending on the signed currents. For an allowed passive inductance matrix, the total energy remains nonnegative. Unlike the ideal transformer element, the coupled pair stores finite energy. Even perfect coupling does not remove its magnetizing energy state. Real magnetic saturation, hysteresis and bias dependence also mean that a constant-L energy formula is not valid over every operating condition.

With imperfect coupling, the terminal voltage ratio is not generally fixed by a turns ratio. For example, with winding 2 open, i₂ = 0 and v₂/v₁ = M/L₁ for a changing primary current in this ideal lossless pair. Using √(L₁/L₂) as a turns ratio is only appropriate when leakage is negligible and the inductances correspond to the same common flux path.

Worked example: induced voltage and series connection

Choose L₁ = 100 µH, L₂ = 25 µH and k = 0.8. Then:

With winding 2 open and primary current rising at 1 A/µs, the winding voltages are v₁ = 100 V and v₂ = 40 V. The open secondary has voltage but no delivered current; power is going into the magnetic energy associated with the primary current.

Connect the windings in series, carrying one physical path current I:

At 2 A series current the aiding pair stores 410 µJ and the opposing pair 90 µJ. These values also follow by substituting the signed winding currents into the full coupled-energy expression.

This is the engineering consequence of the dots: the same two windings can present very different inductance when reconnected. Series opposing does not generally mean zero inductance. For equal windings L₁ = L₂ = L, it gives 2L(1 − k); zero occurs only in the ideal k = 1 limit.

Open/short measurements and leakage

With winding 2 open, the ideal input inductance is L₁. With winding 2 ideally shorted, v₂ = 0 requires a secondary current slope that opposes the primary contribution. The resulting input inductance is:

The example gives 36 µH, not the 45 µH of series opposition: these are different terminations. Open/short measurements give the estimate:

The 36 µH quantity is the short-circuit input inductance for this ideal pair. It is not automatically an individual winding leakage branch in every transformer equivalent circuit. Real measurements also depend on shorting-lead impedance, winding resistance, frequency, core bias and capacitance.

Where it is used

• Flyback: magnetizing energy is stored in one interval and delivered through the other winding in another interval. Use an energy-storage magnetic model with flux reset.
• SEPIC and Ćuk: coupling can change winding ripple and component requirements; derive the result from the winding voltages and dot references of the actual topology.
• Coupled multiphase buck: winding orientation determines whether relevant phase-current components reinforce or cancel magnetic flux. Tight coupling alone does not guarantee lower ripple in every mode.
• Common-mode choke: arrange the intended outgoing and return currents to oppose their core flux, while common-mode currents reinforce. For equal windings, the per-winding modal factors are L − M and L + M, respectively, under the chosen current references. A two-wire loop measurement can introduce an additional factor of two; state which current and voltage define the measured inductance.

Thermal current rating, combined winding ampere-turns, saturation, leakage energy and insulation all need consideration in a real component. Analog Devices' coupled-inductor modelling article provides a SEPIC example; Coilcraft's coupled-inductor guide discusses the physical component and coupling tradeoffs.

2.6 Real transformer: voltage drop, losses and operating limits

Why the turns ratio is not enough: it relates the internal induced voltages. Winding drops separate those voltages from the terminals; excitation current also flows when the secondary is open. Start with section 2.4's ideal element, then include the effects needed at the operating frequency.

A circuit with separate winding impedances

For sinusoidal steady state, use RMS phasors and refer all secondary impedances to the primary. Define:

The primary winding impedance Z₁ precedes the excitation branch; the referred secondary impedance Z′₂ follows it. This T equivalent circuit retains the difference between primary current I₁ and referred delivered load current I′₂:

The physical delivered secondary current is I₂,out = nI′₂. In open circuit, I′₂ = 0 but I₁ = I₀ generally remains nonzero. The real part of excitation admittance accounts for core dissipation; its inductive part accounts for reversible magnetic energy storage. The internal induced voltages obey E₁ = nE₂, while loaded terminal voltages generally do not obey V₁ = nV₂.

This is often called the exact equivalent circuit in introductory transformer analysis: exact within the chosen linear lumped model. It still omits saturation, distributed capacitance, and frequency-dependent loss. Section 2.4's combined-series circuit is a further approximation; retaining separate branches avoids assigning secondary copper loss to the no-load primary current.

Worked sinusoidal reference: compare ideal and real operation

Keep the ideal example's 48 V RMS input, n = 4 and 6 Ω resistive load. Choose a 50 Hz sinusoidal teaching model with the following winding parameters; these are illustrative values, not a component specification. Use this as the phasor-circuit reference; section 2.8 provides the main power-converter example with approximately 5 kW of square-wave power transfer.

At 50 Hz, Z₁ = 1 + j0.628 Ω, Z′₂ = 1.28 + j0.628 Ω, Z′L = 96 Ω and Ym = 0.0004167 − j0.0015915 S. Substitution gives:

Compute losses with the currents of the respective branches:

The model's open-circuit primary current is 78.9 mA RMS and its no-load active input power is 0.964 W. Multiplying 48 V by the current magnitude gives apparent power, not active power: the magnetizing current is largely reactive. It nevertheless contributes to primary copper heating. At light load, core loss consumes a large share of input power; as load rises, copper loss increases approximately with current squared.

The figure varies only the resistive load and holds the model parameters fixed; 100% on its horizontal axis means the chosen 6 Ω reference load, not a hardware rating.

Define voltage regulation at the same input voltage and frequency:

A lagging-power-factor load generally adds leakage-reactance voltage drop. A leading load can reduce the drop or produce negative regulation. Resistive voltage-divider reasoning alone cannot describe those phasor effects. Rose-Hulman's transformer notes, pages 7–9, cover this circuit and the efficiency/regulation definitions.

Flux, saturation and waveform dependence

For induced primary voltage e₁, the general relation remains:

For a sinusoidal flux centred around zero, and for a symmetric bipolar square induced voltage, respectively:

The square-wave voltage is its constant magnitude in each half-period. Both expressions assume centred periodic flux; DC offset or incomplete reset requires tracking absolute B as well. The sine formula's 4.44 factor must not be applied to arbitrary PWM. At unchanged induced voltage, reducing frequency increases flux swing.

Saturation reduces incremental magnetizing inductance and can cause a steep current rise. Switching near an unfavourable mains phase, together with remanent flux, can also cause inrush even when the final periodic operating point is acceptable.

Higher switching frequency allows fewer turns or a smaller core area for the same voltage and flux swing, but raises other constraints. Core loss depends on material, frequency, temperature and the actual B waveform. Skin and proximity effects make winding AC resistance frequency dependent; for a linear harmonic loss model, winding loss is a sum of Iₖ,rms²Rac(kf).

Section 2.7 develops this conductor-loss calculation. Insulation thickness, winding arrangement and cooling also matter. A constant Rcore and DC winding resistances cannot predict all of these effects. TI's Power Transformer Design note discusses the loss and thermal tradeoffs.

Switching edges: leakage energy and capacitive feedthrough

At a switching transition, leakage inductance resists rapid current change. Its stored energy must transfer to another element or dissipate:

As a separate switching example, 2 µH carrying 3 A stores 9 µJ. If one such event per 100 kHz cycle is fully dissipated in a clamp, its average contribution is 0.90 W. If that energy instead charges an initially uncharged ideal 200 pF capacitor, the energy-only estimate gives 300 V and a natural frequency of 7.96 MHz.

These are model scales: initial capacitor voltage, rail connections, nonlinear device capacitance, damping and the clamp determine the actual switch peak. Do not simply add 300 V to a rail without deriving the circuit.

Interwinding capacitance provides a displacement-current path across galvanic isolation:

For 20 pF subjected to 10 V/ns, the instantaneous current scale is 0.20 A. This is edge current, not continuous load current. Its return path determines common-mode EMI. Interleaving windings can reduce leakage while increasing interwinding capacitance; electrostatic shields can redirect capacitive current but need a defined connection.

Insulation and dielectric distance affect both capacitance and isolation construction, linking back to section 3.3. These capacitances are omitted from the 50 Hz T model above; add them when analysing fast switching edges.

How the model parameters are estimated

• Winding resistance measurement: estimates R₁ and R₂ at the measurement temperature; operating-temperature and AC loss can differ.
• Open-circuit test: at the intended sinusoidal frequency and voltage, measure Voc, Ioc and Poc. When series drops and no-load copper loss are small, Rcore ≈ Voc²/Poc, Im ≈ √(Ioc² − (Poc/Voc)²), and Lm ≈ Voc/(ωIm).
• Short-circuit test: with one winding shorted, apply a reduced voltage at the test frequency to obtain the selected test current. With excitation current negligible, Zeq ≈ Vsc/Isc, Req ≈ Psc/Isc² and Xeq ≈ √(Zeq² − Req²). These give the combined series parameters referred to the driven side; they do not uniquely split primary and secondary leakage.

The open/short estimates and their assumptions are described in Rose-Hulman's notes, pages 12–13. A switching-frequency component also needs impedance, capacitance, loss and bias information relevant to its operating waveforms.

Classroom check: why can the loaded real transformer draw more primary current than the ideal example while delivering less power? Its primary current supplies the referred load, core loss and magnetizing excitation; winding losses also consume input active power. Use phasor addition for currents and an active-power balance for watts.

2.7 Skin effect: why copper resistance depends on frequency

Physical idea: a changing current produces a changing magnetic field inside the conductor. The induced electric field redistributes current toward the surface. At low frequency, current density in a uniform round copper wire is approximately uniform; at high frequency, much of the interior carries little AC current.

The same total RMS current then produces more resistive heating. This is electromagnetic diffusion, rather than an increase in copper's intrinsic resistivity caused by frequency alone.

Skin depth and useful copper numbers

For sinusoidal excitation of a good conductor with resistivity ρ and permeability μ:

Near a flat conductor surface, with x measured inward and an exp(jωt) phasor convention:

At one skin depth, current-density amplitude is 1/e ≈ 37% of its surface value; it is not abruptly zero beyond δ. This exponential profile assumes a locally flat, sufficiently thick conductor. A round wire whose radius is comparable to δ needs the cylindrical solution used below.

For the teaching calculations, take copper at approximately 20 °C with ρ = 1.724 × 10⁻⁸ Ωm and μ ≈ μ₀. Then:

For this wire, δ equals its radius at about 17.5 kHz; this is a scale, not a sharp onset frequency. Larger busbars can exhibit significant skin effect even at mains frequency. Temperature changes resistivity, resistance and skin depth, so state the temperature when comparing values. TI's winding-loss note, pages 1–3, introduces skin depth and the redistribution mechanism.

Worked example: one metre of round copper wire

Take a straight, uniform 1 m conductor with diameter d = 1.00 mm and radius a = 0.50 mm. Assume a distant return, circular symmetry and no proximity effect:

When δ is much smaller than a, an effective conducting area of approximately 2πaδ gives:

This high-frequency approximation must not be used at low frequency, where it can incorrectly predict resistance below RDC. The figure and table instead use the cylindrical diffusion solution, valid through the transition:

I₀ and I₁ here are modified Bessel functions, not winding currents. Zint includes the wire's internal magnetic reactance; external loop inductance must be added separately. Students need the physical limits and numerical results; the companion script evaluates the special functions.

These losses apply to the one conductor. A separate return conductor also dissipates power; bringing the return close changes the current distribution through proximity effect. A winding with the same wire diameter and copper length need not have these isolated-wire AC resistances.

PWM currents: apply the resistance to each frequency component

Skin depth is defined for a frequency component. For a periodic nonsinusoidal current, Fourier analysis and a linear conductor model give:

For the 1 m wire carrying 10 A DC plus a 2 A RMS, 1 MHz sinusoidal ripple, total RMS current is √(10² + 2²) = 10.198 A. The loss is:

Using total RMS current with RDC would give only 2.283 W, about 10.5% below the calculated loss. Applying the 1 MHz resistance to the entire DC current would also be wrong. A real PWM waveform has multiple harmonics; calculate their current amplitudes and losses rather than assigning one skin depth from the switching edge alone.

In a multiwinding component, proximity losses can depend on the amplitudes and phases of currents in the other windings as well.

Skin effect, proximity effect and conductor choice

Skin effect describes redistribution by a conductor's own alternating field. Proximity effect describes additional redistribution caused by nearby current paths and their fields. In a multilayer transformer winding, proximity losses can dominate. Their size depends on layer arrangement, winding currents and air-gap fringing fields. The isolated-wire curve therefore establishes a reference, not a complete winding-loss prediction.

For an equal-copper-area comparison, 100 strands of 0.10 mm diameter contain the same copper cross-section as one 1.00 mm wire. At 1 MHz, the isolated 0.10 mm strand has RAC/RDC ≈ 1.0068, versus 4.045 for the solid 1 mm wire. With equal strand currents and the same 1 m strand length, the skin-only bundle estimate is 22.10 mΩ.

This illustrates the benefit of subdivision; it is not a full litz-winding prediction. The bundle's outside diameter is larger because of insulation and packing, and actual transposition increases strand length. Elektrisola's litz-wire technical information describes strand insulation and construction; Ansys's litz-wire modelling documentation states the ideal transposition assumptions.

On a PCB, compare the copper thickness with δ, then include the return and layer fields. At 100 kHz, 35 µm copper is much thinner than the 209 µm skin depth; thickness alone does not suggest severe skin effect, but geometry can still cause proximity or edge crowding.

Skin effect concerns penetration into copper; dielectric distance concerns separation between conductors and changes capacitance, external inductance and proximity fields. They are different dimensions of the same physical layout.

Classroom check: would doubling a thick wire's diameter halve its resistance? For DC it ideally reduces resistance by four; in the strong skin-effect limit, isolated-wire AC resistance is approximately halved because the perimeter doubles. Check which regime applies first.

2.8 Proximity effect and a high-power square-wave transformer

Physical idea: neighbouring turns impose a magnetic field on a conductor. The induced currents can reinforce transport current on one surface and oppose it elsewhere, creating additional copper loss. A conductor can even carry zero net transport current while supporting local eddy currents and heating. Thus, total ampere-turn cancellation in a transformer does not imply zero field everywhere in its winding window.

Skin effect already makes a thick conductor costly at high frequency. Proximity effect adds sensitivity to where the turns and their return ampere-turns are placed. A single-layer winding avoids the accumulation across many layers, but still experiences fields from adjacent turns and the other winding. The two calculations below deliberately distinguish these mechanisms.

Specify power transfer and the current waveform first

Use a 1:1 transformer with four primary and four secondary turns, driven from a bipolar bridge. At the load terminals, specify the following operating point:

The load voltage and current have matching, symmetric, flat-topped waveforms with finite transitions. An ideal square wave is their zero-transition-time limit. Here the resistive load makes current follow voltage; a square-wave transformer voltage feeding a different circuit need not produce square-wave current.

During a linear transition from −I to +I, mean squared current is I²/3. Two transitions occur each period, so:

The zero-transition-time limit is 5.000 kW. Mean signed voltage and current are zero, but their product has positive mean. Positive and negative half-cycles both deliver power.

This calculation specifies the load waveform and estimates winding loss at that operating point. The source must provide additional voltage headroom and active power for winding drops and losses. It is not a transient simulation of a fixed 100 V DC bus and a lossy transformer.

Magnetizing current is neglected in the load-current comparison. With a 500 mm² effective core area, applying the specified waveform to an ideal induced-voltage winding gives a centred flux peak of approximately 0.0613 T. Actual induced voltage, core loss, material limits, commutation and temperature require a complete converter design.

Step 1: high loss from skin effect, even with one layer

First wind each four-turn winding in a single radial layer of solid 2.00 mm diameter round copper wire. Each winding contains 0.80 m of copper; both together contain 1.60 m. The combined DC resistance is 8.780 mΩ. Evaluated with the actual 49.33 A RMS current, the constant-resistance heating estimate is:

This is a DC-resistance estimate of AC heating, not a proposal to apply DC voltage to the transformer. At 200 kHz, copper skin depth is only 0.148 mm, much smaller than the wire's 1 mm radius.

Represent each rounded square waveform as a bipolar square convolved with a unit-area box of duration tr. For odd harmonic k, define sinc(x) = sin(πx)/(πx):

Use the cylindrical wire resistance from section 2.7 at each kf₀. The result is:

The rounded square's skin-only loss is 4.35 times the DC-resistance estimate, and approximately 19.4% above the same-RMS sinusoidal-current case. The comparison with the sinusoid isolates current-waveform loss; it does not assume identical power transfer or flux for the two voltage drives. This first calculation excludes proximity effect and uses the isolated-wire resistance as a reference.

Single-layer construction therefore does not guarantee a low-loss high-frequency winding; the full winding can dissipate more than this skin-only estimate.

Step 2: keep the operating point, compare layered winding arrangements

Now consider a separate conductor construction: four one-turn radial layers per winding. Each foil turn is 20 mm wide and 0.20 mm thick, giving 4.000 mm² copper area, with the same 0.20 m mean turn length. Compare two orders across the window:

• Grouped: P P P P S S S S.
• Interleaved: P S P S P S P S.

All four P turns are connected in series, as are all four S turns. Interleaving changes their physical order, not the 4:4 electrical turns ratio. The foil comparison holds conductor dimensions, copper length, load waveform and turn counts fixed. Its copper area differs from the single-layer round-wire reference's 3.142 mm², so the two geometries are not an arrangement-only comparison.

In a one-dimensional winding-window model of width b, a layer carrying current Iₖ changes tangential field by Kₖ = Iₖ/b. Set the outer load-current field to zero and neglect magnetizing current. At the 50 A reference and b = 20 mm, K = 2500 A/m. The grouped stack's boundary fields are:

The interleaved stack instead gives:

Each harmonic scales these fields with its own signed winding-current phasor. A foil layer's mean boundary field Havg = (Hleft + Hright)/2 drives its proximity contribution. Summing Havg² across eight layers gives 42K² grouped and 2K² interleaved: a factor of 21 in the foil model's proximity term, even though total primary and secondary ampere-turns cancel in both stacks.

Why proximity loss remains in the interleaved case: the field alternates between zero and K rather than disappearing. Each turn still has a nonzero mean field. More interfaces can also increase primary-secondary capacitance and consume space for insulation; minimum copper loss is only one design objective. TI's winding-loss note, especially its transformer and interleaving examples, provides the physical background for these field profiles.

Step 3: replace each foil turn with ideal transposed litz

For a nearly equal copper area, use 800 individually insulated strands of 80 µm diameter per turn. Their total copper area is 4.021 mm². Retain the same electrical turn counts and 0.20 m strand length per turn for the comparison. Assume equal transport-current sharing and ideal transposition within each turn.

Model the macroscopic field as varying linearly across each litz turn, with a locally uniform applied field at each strand position and no bundle shielding.

The script calculates isolated-strand transport/skin loss and the cylindrical eddy-current response to the applied transverse field, then averages over strand positions and sums the strands and current harmonics. Full transposition samples the mean of H², not just the square of mean H. For the specified linear field profile:

The litz field-square sums are therefore (128/3)K² grouped and (8/3)K² interleaved, a ratio of 16. The applied-field proximity term remains; the calculation does not merely substitute the fine-strand skin resistance and assume all remaining AC loss vanishes.

All entries are combined primary-plus-secondary copper losses at the specified load waveform. The foil and litz DC-resistance estimates are 16.78 W and 16.69 W respectively. Core loss, bridge loss and rectifier loss are outside the table, so these numbers are not total converter loss or efficiency.

Engineering conclusion for this example: interleaving strongly reduces the applied field, while subdivision into fine insulated strands reduces conductor eddy loss. They address different parts of the problem. Under the specified model, interleaved foil even outperforms grouped ideal litz. Litz selection therefore needs the harmonic spectrum and winding field, not just a strand-diameter check at f₀.

The litz numbers are idealized applied-field estimates, not predictions for a purchased bundle. Real bundle packing and shielding, local strand-to-strand fields, incomplete transposition, terminations, twist length and departures from the assumed linear macroscopic field change the result. A transposed bundle also occupies more space than its copper area and usually uses more strand length than the winding centreline length.

Consult Ansys's litz modelling assumptions and Elektrisola's construction information when moving beyond this teaching comparison.

Optional model detail: reproducible loss rather than a guessed multiplier

For a foil of thickness t, width b and conductor length ℓ, solve d²H/dx² = q²H with q = (1 + j)/δ and the two specified boundary fields. With RMS harmonic quantities, let ΔH = Hright − Hleft and Havg = (Hleft + Hright)/2. Integration of ρ|J|² over the conductor gives:

The first term is the transport/skin contribution, the second the proximity contribution. Their cross term integrates to zero in this symmetric one-dimensional model. Sum the layers and the odd harmonics. The script independently checks the result by integrating the complex current-density profile and its Joule heating.

For a fine round strand of radius a in a weakly screened, uniform transverse field H, the low-frequency applied-field limit is:

The numerical litz calculation uses the full cylindrical applied-field response through the skin transition, rather than extrapolating this ω² approximation to every harmonic. Harmonic sums through k = 1999 were checked against k = 3999; the reported total losses change by less than 0.002%. This checks numerical truncation within the model, not agreement with hardware.

The field model assumes broad layers, uniform tangential boundary fields, negligible fringing and fixed room-temperature copper resistivity.

Classroom checks: why does zero total load ampere-turns not imply zero copper eddy loss? Fields can remain between and inside winding layers. Why is a litz bundle still lossy in a large external field? Insulated strands still support internal eddy currents, and imperfect construction can add further losses.

Winding choice. Interleaving can reduce leakage and proximity loss, but changes capacitance and insulation geometry. Compare it with the grouped winding under the same waveform and constraints. Choose from the combined loss, coupling and construction requirements rather than one curve.

3. Capacitive coupling on a PCB: why edge speed matters

3.1 From prepreg thickness to displacement current

For overlapping conductors separated by a thin dielectric:

Consider a broad 1 mm wide conductor overlapping another conductor for 10 mm, separated by 0.10 mm of dielectric with assumed $\varepsilon_r=4$. The overlap area is 10 mm², giving approximately 3.54 pF. This is a parallel-plate estimate; fringing and the actual stackup require a field model for accurate design.

For a prescribed digital edge of 3.3 V in 1 ns, with the other conductor held approximately stationary:

A few picofarads can therefore inject milliamperes. The edge rise time, rather than only the clock frequency, determines the fast current.

Reference plane versus victim node. If the second conductor is an ideal grounded plane, this is return current into that plane. Its voltage does not change in the ideal model. A real plane or shared return impedance can develop ground bounce. Coupling into a high-impedance signal or power node is a different circuit and can generate a much larger voltage.

A continuous grounded shield plane also changes the coupling geometry; do not assume that a direct mutual capacitance remains unchanged through it.

3.2 A defined lumped victim model

Use an ideal aggressor voltage $v_a$, a mutual capacitance $C_m$ into a victim node, and a victim impedance $R_v\parallel C_v$ to its quiet reference:

Kirchhoff's current law gives:

Therefore:

The aggressor-voltage to victim-voltage path is high-pass, with high-frequency limit $C_m/(C_m+C_v)$. The injected-current to victim-voltage impedance is low-pass:

These two views explain the apparent contradiction: fast voltage edges couple strongly, while the victim capacitance limits the voltage generated by a given high-frequency injected current.

For $C_m=3.54$ pF, $C_v=10$ pF and $R_v=50$ Ω:

For an aggressor ramp of duration $t_r$, starting from zero victim voltage, the voltage at the end of the edge is:

After the edge it decays exponentially with time constant $\tau_v$. For an ideal instantaneous edge the initial jump approaches the capacitive-divider value, approximately 0.863 V here. The finite 1 ns edge gives the smaller result above because the resistance conducts during the edge.

Design interpretation: reduce overlap or mutual capacitance, control edge speed where permitted, provide an intentional return path, reduce victim impedance, and place suitable filtering near the victim. Adding capacitance reduces a fast voltage jump but can lengthen its decay; calculate both amplitude and duration. A long coupled line needs a distributed coupled-line model including mutual inductance.

The lumped example demonstrates the mechanism rather than predicting near-end/far-end crosstalk on an arbitrary PCB.

3.3 Dielectric distance: make the separation explicit

Here h is the finished dielectric thickness between the two facing copper surfaces, measured perpendicular to the layers. It is not the copper thickness, lateral trace spacing, or the overall board thickness. In a multilayer PCB, use the relevant finished core/prepreg spacing and the material's applicable permittivity; εr = 4 is the teaching assumption here, rather than a universal PCB value.

For fixed overlap area and permittivity:

Halving the separation doubles the plate-model capacitance and the approximate current into a stationary victim/reference. With the previous 10 mm² overlap, εr = 4, 3.3 V / 1 ns edge, and the same 50 Ω ∥ 10 pF victim:

The current column is a capacitance estimate with a stationary victim. The victim-voltage calculation instead uses the coupled differential equation in section 3.2, allowing the victim to move. Its peak does not simply double when h halves, because capacitance also changes the time constant and the capacitive-divider ratio.

The figure holds the other circuit parameters fixed to isolate this effect. As separation becomes comparable with conductor width, fringing weakens the accuracy of the plate approximation.

An intentional reference plane gives a different design tradeoff. Bringing a signal or power conductor closer to its return plane increases its capacitance to that reference and reduces loop inductance. For wide parallel conductors in a uniform medium:

Thus thinner dielectric to a continuous quiet reference is often helpful for field confinement and low-inductance current return. Thinner dielectric directly between an unshielded aggressor and a sensitive victim increases mutual coupling. Always identify which conductors the distance separates. In the ideal uniform TEM model, L′C′ = µε, so changing h alone changes impedance but not propagation velocity; changing dielectric permittivity changes velocity as well.

Distance through insulation, clearance and creepage are separate concepts. Thickness h is a path through solid dielectric; clearance is an air path and creepage follows an insulating surface. A uniform-field estimate is E ≈ ΔV/h: for example, 400 V across 0.10 mm corresponds to 4 kV/mm.

This is a field calculation, not a voltage-withstand rating. Material, manufacturing quality, edge geometry, voltage waveform and the applicable insulation requirements determine a qualified design. No universal safe mm/kV rule follows from the capacitance formula. See TI's explanation of distance through insulation.

Spacing choice. More separation reduces the plate-model coupling capacitance. It also changes the board geometry and stackup. If that change is impractical, compare reducing overlap or edge speed. Recalculate the victim response; injected current alone does not settle the choice.

4. Worked design exercise: how close must the CPU's source be?

This exercise emulates a fast die-side CPU load transient. It does not assert the measured slew rate of a particular processor. The regulator, board, package and die capacitors supply different frequency ranges.

Given

• Nominal CPU rail: 1.00 V, with ±30 mV allowed deviation.
• Initial rail is settled at 1.00 V under a 40 A load.
• Load rises from 40 A to 60 A in 20 ns: an incremental 20 A ramp.
• First model: no local capacitance, an ideal source, negligible resistance, and a supply/return pair with assumed loop $L'=1$ µH/m.
• Assign the entire 30 mV downward deviation budget to this one mechanism. The full 60 mV tolerance band is not available from an initially nominal rail.

Step 1: inductance and distance limit

With the same assumptions, a 1 mm connection would produce a 1 V inductive drop. The result exposes the failure of a remote source alone to supply this fast current ramp. The immediate source must include local stored energy, often on the die or in the package.

It is not a board-placement rule requiring the VRM to sit 30 µm from the CPU. Different interconnect geometry changes $L'$, and capacitance changes the circuit.

Step 2: negligible inductance, maximum Thévenin resistance

Retain the initially regulated 1.00 V operating point and allocate the 30 mV incremental droop to resistance alone:

This is an incremental source-impedance requirement around the settled operating point. If instead an uncompensated ideal source is fixed at 1.00 V and all absolute DC drop at 60 A must fit within 30 mV, the resistance bound is 0.50 mΩ.

Step 3: where the capacitors enter

The charge deficit determines capacitance:

If upstream current stays at its initial value during the 20 ns linear ramp, the deficit is triangular. Its charge is 0.20 µC; capacitance alone would need at least 6.67 µF for 30 mV. If a capacitor must subsequently deliver the full extra 20 A for a separate 100 ns interval, that interval alone needs 66.7 µF. Real selection also includes capacitance derating, ESL, ESR, package impedance and resonances.

The mechanisms share the budget; they cannot each consume the full 30 mV simultaneously:

In frequency-domain design the same idea becomes a target impedance over a specified frequency band:

The required band and allocation between board, package and die are part of the specification. See AMD's target-impedance guidance and Intel's board-design guidance.

4.1 Classroom riddle: why put 10 nF and 100 nF beside a digital IC?

Start with the question, then choose the disturbance. Is ripple arriving from the supply, or is switching current being drawn by the IC? These are different inputs to the same network. A CPU/GPU supply current can contain sharp pulses and many harmonics; it need not be a literal clock-frequency square wave. The following model isolates the mechanism rather than representing a measured processor.

Let Zs be the regulator-plus-interconnect impedance seen from the chosen IC supply port. Let ZC include the local capacitor's ESR and complete loop inductance. An independent small-signal current sink represents the load-current disturbance; a separate ZIC can represent the IC's incremental port impedance. First take ZIC sufficiently large to omit it. With the supply-noise voltage set to zero:

The ideal capacitor would be 1/(jωC), but a first practical model is:

If ZIC is retained, include it in the parallel admittance when calculating the response to the independent current disturbance. Do not use the same load-current response once as an independent source and again inside ZIC. An IC's DC ratio V/I is not generally its high-frequency impedance: 0.8 V / 100 A = 8 mΩ is a static operating-point ratio, not a measured ZIC(f).

Quiz A — make the source ideal at the IC pins. Set Zs = 0. The load-current-induced voltage ripple is zero in this ideal model, with or without the capacitor. The ideal source supplies the disturbance current; a capacitor across a perfectly fixed voltage cannot further improve that voltage. This does not describe a remote regulator separated from the die by a package, vias and traces.

Quiz B — apply supply-voltage ripple instead. With the independent load-current disturbance set to zero and ZIC omitted:

For Zs = 0 this ratio is one: a shunt capacitor does not attenuate ripple imposed by an ideal voltage source at its own node. A finite series impedance can create source-to-load filtering. The identical algebra above describes two different measurements: voltage-noise transfer and the fraction of IC disturbance current flowing upstream. State the excitation and measurement before saying “attenuation.”

Quiz C — add the connection and move the capacitor. Use 1 nH/mm, not nΩ/mm, as the specified two-wire-loop estimate from section 2.3. Inductance becomes impedance through jωL; 45 nH has reactance about 283 Ω at 1 GHz. This number is not a universal PCB-trace impedance, especially when the interconnect is electrically long.

Local capacitance can provide fast load current while the upstream path changes current more slowly. Keep the capacitor-to-power-pin-and-return loop inductance small. “Close” includes the return, vias, package and mounting geometry. A capacitor directly underneath the IC can provide a short loop when the stackup and via arrangement support it; placement on the opposite face is not inherently best. TI's processor-PDN layout guidance, section 3, discusses mounting and spreading inductance.

Numerical comparison, separate from the 100 A exercise below: choose a small-signal source path of 20 mΩ + jω·5 nH, a 100 nF capacitor with 10 mΩ ESR, and total capacitor-loop inductance of either 0.5 nH or 5 nH. A third case parallels the close 100 nF with 10 nF, 20 mΩ ESR and 0.5 nH loop inductance. These are authored lumped examples, not a GPU rail design.

With 0.5 nH, the 100 nF and 10 nF branches have self-resonances at 22.5 MHz and 71.2 MHz. The 100 nF branch's impedance at 1 GHz is approximately 3.14 Ω, dominated by inductance. A smaller capacitance can move branch resonance upward, but paralleling capacitor values can also create antiresonance peaks.

Select values, packages and mounting from the complete impedance profile, rather than assuming that adding 10 nF always improves 100 nF.

The plots show conducted current division and port impedance. They do not predict radiated-emission attenuation in dB. Radiation also depends on loop area, return discontinuities and common-mode paths. A passive PDN resonance peak is also not, by itself, proof of control-loop instability; section 12.6 shows how an actively regulated load can destabilize an input filter.

Which capacitor helps? Start by shortening the mounted path of the 100 nF capacitor. The 10 nF addition is a separate candidate, not an automatic improvement. Keep both only if their combined impedance improves the required band without unacceptable peaking. Otherwise, the single close capacitor is the simpler choice.

4.2 Board-diagonal quiz: will a 1 GHz signal disappear?

Given: a square board with 10 cm² area, components at opposite corners, and an approximately diagonal route. A 3 cm × 3 cm board would instead have 9 cm² area; neither description means a 10 cm × 10 cm board.

First distinguish plane capacitance from trace capacitance. If two overlapping planes use the entire 10 cm² area, εr = 4 and h = 1 mm between copper surfaces, their plate-model capacitance is:

At 0.10 mm dielectric separation, the same estimate becomes 354 pF. Total PCB thickness is not necessarily the signal-to-reference spacing. A signal trace does not use the full board area as its plate: its width, reference geometry, dielectric and fringing fields determine its capacitance and inductance. One cannot infer “45 nH and a few hundred pF” for that trace from board area and diagonal alone.

Does the voltage-divider arithmetic work? If we deliberately build an ideal lumped series 45 nH followed by a shunt 300 pF capacitor, unloaded, its calculated gain at 1 GHz is approximately 0.00188, or −54.5 dB. That is the result for the specified lumped LC circuit. It does not establish that distributed PCB traces behave as one inductor followed by the whole board capacitance at their far end.

A counterexample with a defined signal line. Choose a uniform, lossless 50 Ω line with effective relative permittivity 4 and a matched 50 Ω receiver. This is an illustrative line, not a stackup extracted from the incomplete board geometry:

At 1 GHz the electrical length is about 107.4°. The distributed line therefore cannot be replaced by one end-loaded LC cell. With a matched load:

Its magnitude is one: the receiver sees a delayed signal. The ratio is measured from the line entrance, so any source-resistance voltage division during launch is outside this ratio. A real PCB adds frequency-dependent conductor/dielectric loss; a mismatched receiver adds reflections. Neither implies that a 4.5 cm path automatically removes a 1 GHz signal.

For CPU-to-RAM signals, use driver/receiver models, the reference path, line impedance, delay and termination. Edge rise time and harmonics matter as well as clock rate. Intel/Altera's signal-integrity white paper covers distributed interconnects, impedance mismatch and loss. Supply decoupling across a power rail and adding capacitance to a data signal are different circuit interventions.

4.3 CPU/POL exercise: translate tolerance into an impedance budget

Use a teaching scenario, not a claimed Intel or NVIDIA device limit: a nominal 1.00 V rail, initially settled at nominal, with 30 mV allowable downward deviation and an additional 100 A load-current demand at the defined IC port. The one-sided voltage budget gives the target-impedance scale:

This applies to the total PDN seen at that port over the specified frequency range. It is a screening/design target, not a guarantee of peak transient voltage for every waveform. The DC/DC's output impedance alone is insufficient when interconnect and local storage matter. In a simple lumped model, Zs = Zreg + Rpath + jωLpath, with local capacitor branches connected at their actual locations.

A die-side current requirement also needs the package and die network; it must not silently be moved to a board-side port.

Resolve the slew-rate unit before calculating distance. Allocate all 30 mV to inductance alone for this comparison, neglect capacitors and resistance, and retain the assumed loop L′ = 1 nH/mm:

A millisecond versus a microsecond changes the inductance allowance by a factor of 1000. These distances expose the limit of a remote-source-only model; they do not prescribe practical VRM placement or apply unchanged to closely spaced power/return planes.

Step 2 — negligible inductance: if the full 30 mV incremental drop is resistive, total Thévenin resistance must be at most 0.30 mΩ. If instead we divide the budget into 10 mV for resistance, 10 mV for inductance and 10 mV for capacitor charge deficit:

• Total incremental resistance allowance is 10 mV / 100 A = 0.10 mΩ. With an assumed path resistance of 0.04 mΩ, only 0.06 mΩ remains for the regulator's resistive contribution in this simplified model.
• At 100 A/µs, the inductance allowance is 10 mV / (100 A/µs) = 0.10 nH, corresponding to 0.10 mm only under the assumed loop-inductance-per-length model.
• A 100 A rise over 1 µs, while upstream current remains at its initial value, leaves a triangular 50 µC charge deficit. Limiting the capacitive contribution to 10 mV requires 5 mF effective capacitance. If the upstream current responds during the ramp, integrate the actual smaller deficit; a different waveform or interval gives a different result.

This is why 10 nF and 100 nF local capacitors address a different portion of the transient spectrum from bulk storage and the closed-loop POL regulator. Account for actual DC-bias derating, ESR, ESL and the handover between board, package and die. Do not assign the full voltage allowance independently to every mechanism and then sum them.

Connection to published methodology: the Intel/Altera PDN Tool User Guide, sections on target impedance and decoupling, uses allowable ripple, transient current and a target frequency range. It is FPGA PDN guidance, not a CPU or NVIDIA GPU electrical specification. To make this a device-specific assignment, provide the exact processor and rail documentation, its allowed DC/load-line/AC deviation, transient current waveform and the port where each requirement is defined.

Then replace the teaching values and verify both impedance and time-domain response.

Where to spend the voltage budget. Use local energy storage for the fast load change and a short path to replenish it. The remote source alone cannot meet the fastest stated slew under the assumed inductance per length. If the actual device has a slower transient, recalculate the allocation before adding capacitors. These distance estimates are not layout dimensions for a named processor.

5. Average and RMS: define these before calculating power

5.1 Definitions and the three useful numbers

For a real periodic waveform of period $T$:

Average is signed. RMS is nonnegative and expresses an equivalent resistive-heating effect. The rectified average $\langle|x|\rangle$ is another quantity; it must not be confused with the signed average of a bipolar signal.

Remember √2 for a sine, √D for a rectangular pulse, and √12 for peak-to-peak triangular ripple. They follow from integration, not from a universal conversion between peak and RMS.

Square-wave distinction: a ±A square wave has RMS A. A 0/A square wave at 50% duty has average A/2 and RMS A/√2. Always draw the zero level and state the duty cycle.

5.2 DC plus ripple and zero intervals

For a waveform consisting of a DC component plus a zero-mean AC component:

For a DC inductor current with triangular peak-to-peak ripple:

For 10 A DC and 4 A peak-to-peak triangular ripple, the total RMS is approximately 10.066 A. The ripple RMS is only 1.155 A. In an ideal buck with an approximately constant load current, the output capacitor carries the ripple component, rather than the 10 A DC component.

If a known waveform segment occupies only a fraction D of the complete period, with zero elsewhere, its full-period average is multiplied by D and its RMS by √D, relative to the segment's own average and RMS. Mean squares add for orthogonal signals, including DC plus zero-mean ripple, different Fourier harmonics, and two currents that never flow simultaneously.

Existing course reference: the 2025 script, sections 2.3.8–2.3.10 (pages 34–37) and Appendix A, sections 16.1.1–16.1.3 (pages 299–301), contains the corresponding power rules, waveform collection and RMS derivations. These are incorporated here in fresh notation, with sine and square-wave cases made explicit.

6. Active power, reactive power and heating

6.1 Use average current when voltage is constant

When the port voltage is constant at U:

Example: an ideal 12 V input bus supplies 20 A rectangular pulses at 25% duty. The average current is 5 A, so the average input power is 60 W. Its current RMS is 10 A; multiplying 12 V by 10 A would incorrectly give 120 W. This is an input-energy calculation at a constant-voltage port.

A diode approximated by a constant 0.7 V forward drop, conducting those same pulses, dissipates approximately 3.5 W, using 0.7 V × 5 A. If the forward characteristic is instead modelled as a fixed drop plus resistance, both average and RMS current enter the loss calculation.

In general:

Do not multiply averages when correlated voltage and current ripple make the second term significant.

For periodic waveforms, section 10.5 calculates the same average power from synchronized voltage/current FFTs, retaining phase and distinguishing peak from RMS spectral scaling.

6.2 Use RMS current for ohmic heating

For a constant resistance:

With a 20 mΩ conductor or on-state MOSFET resistance, the 20 A / 25% pulses cause:

A constant 5 A current has the same average but causes only 0.50 W in that resistance. Pulsing increases heating by a factor of four here. A capacitor's current can have zero mean while its ESR still dissipates power; for 2 A RMS and 50 mΩ ESR the loss is 0.20 W.

At high frequency, resistance and ESR may vary with frequency and temperature, so harmonic loss calculation may be necessary.

6.3 Active power is not synonymous with loss

Active power is net average energy transfer. It may become useful mechanical power, charge a battery, or become unwanted heat. Converter losses are the unwanted part of this real-power balance:

In periodic operation an ideal inductor or capacitor returns the energy it stores over a cycle. Its net average power is zero, despite nonzero instantaneous power and potentially large RMS current.

6.4 Why reactive current still increases losses

For sinusoidal voltage and current, with lag angle φ:

Reactive power describes cyclic exchange in the ideal reactive part; it is not itself dissipated there. For fixed active power and voltage, the required current rises as power factor falls:

Example: 2.30 kW at 230 V RMS requires 10 A at unity power factor. At power factor 0.5 it requires 20 A. With 0.20 Ω total line-loop resistance, losses rise from 20 W to 80 W. The load still receives 2.30 kW; the conductors and source carry more current.

For distorted waveforms use true power factor:

With purely sinusoidal voltage, this equals displacement factor cos φ₁ times the fundamental-current RMS divided by total-current RMS. Harmonic current can therefore lower power factor even when the fundamental current is in phase. The simple sinusoidal P/Q/S triangle is not a complete decomposition of arbitrary distorted waveforms.

THD, displacement factor and true power factor

For periodic AC without DC, define total harmonic distortion relative to the fundamental RMS component:

Multiply these ratios by 100 for percent. This is the fundamental-referenced convention (THD-F); a total-RMS-referenced instrument setting gives a different number. State the harmonic range and measurement bandwidth. Switching ripple, interharmonics and broadband noise are not automatically included in a line-harmonic THD number. See TI's PFC/THD discussion.

Displacement power factor uses only the fundamental phase difference: DPF = cos φ₁. For sinusoidal voltage, and current with no DC:

For example, DPF = 1 and current THD = 50% give PF = 0.894, not one. With distorted voltage the shortcut above no longer applies, because matching voltage/current harmonics can also transfer active power:

Section 10.5 obtains these signed harmonic powers from synchronized FFTs. DPF, true PF, voltage THD and current THD answer different questions; report all four when assessing a distorted supply.

Why a high PF can hide distortion: the conductance-controlled PFC

A common PFC strategy commands a switching-cycle-averaged line current proportional to the sensed instantaneous line voltage:

Here G is a positive conductance command, approximately constant over a line cycle, set by a slow output-voltage/power loop. With sinusoidal voltage, this produces an in-phase sinusoidal current. With distorted voltage, an ideal tracking loop copies the voltage harmonics into current: Ik = GVk, with matching phase, so THD-I = THD-V within the tracking bandwidth.

It does not need to generate new harmonic orders to cause harmonic current; real control errors and switching add further distortion. Input-voltage disturbances contaminating the current reference are also discussed in TI's PFC guidance.

For exact proportional tracking:

This is why quoting PF alone can feel like “cheating” as a power-quality claim: the number can be perfect while both waveforms contain large harmonics. The PF calculation is correct; it measures normalized voltage–current alignment, not waveform purity or harmonic compliance. Conversely, a controller that extracts the fundamental voltage and commands a clean in-phase sinusoidal current can have THD-I = 0 yet PF below one on distorted voltage.

With no DC, its PF is 1/√(1 + THD-V²).

The design objective therefore matters: proportional conductance gives minimum total RMS current for a specified total active power at a fixed terminal-voltage waveform. A clean fundamental current instead avoids copying supply harmonics. High PF, low THD and minimum frequency-weighted cable loss are related objectives, but are not interchangeable. Specify the actual waveform and harmonic-current requirements when selecting or testing PFC control.

Cable heating: count each harmonic at its own AC resistance

For a linear conductor model at a fixed temperature, with each resistance representing the complete outgoing/return path:

There are two effects. Adding harmonic current while holding the fundamental current fixed increases total RMS and heating even if resistance is constant. Skin and proximity effects can additionally increase AC resistance at higher frequencies, so high-order currents can cost more watts per ampere squared.

The increase depends on conductor size, arrangement and frequency; it is not necessarily large for every cable at low harmonic orders. Sections 2.7–2.8 explain the mechanisms. See also Schneider Electric's harmonic-loss explanation.

Even identical RMS current and THD can produce different heating if their harmonic content occurs at different frequencies. PF alone does not contain the cable's frequency-dependent resistance. At fixed total power and distorted voltage, do not assume that copying harmonics always increases heating: with frequency-independent resistance, proportional current actually minimizes it. Frequency-dependent resistance can reverse that comparison.

Worked counterexample: PF = 1 with greater cable loss

Use a prescribed 50 Hz voltage at the load port with 230 V RMS fundamental and 23 V RMS fifth harmonic, hence THD-V = 10%. Compare two ideal current-reference strategies delivering the same 2.30 kW at that port. Assume a loop resistance of 0.20 Ω at 50 Hz and 0.60 Ω at 250 Hz.

These deliberately illustrative resistance values demonstrate the weighting; they are not a claim about a particular cable. Hold the terminal waveform fixed and exclude PFC internal losses and switching ripple.

For conductance control, G = 2300/(230² + 23²) = 0.043047 S. Its fifth-harmonic current adds approximately 0.588 W of cable heating, enough here to outweigh the reduction in fundamental-current heating. If both harmonic resistances were instead 0.20 Ω, its cable loss would be 19.80 W, below the clean-current case's 20 W.

This makes the limitation precise: perfect PF does not guarantee low THD or minimum AC cable loss, but harmonics do not automatically make conductance control the worse choice under every comparison.

6.5 AC versus DC: what constraint is held fixed?

For in-phase sinusoidal AC:

For constant DC:

Thus DC can transfer more average power when AC and DC share the same peak limits. But the third comparison gives DC 20 A RMS versus only 14.14 A RMS for AC; DC conductor heating is then twice as high for the same resistance. It is not a comparison at equal thermal utilization.

Wires and fuses: continuous conductor heating is principally an RMS-current issue, with additional AC skin/proximity effects where relevant. Fuse operation depends on thermal history, time-current characteristics, fault conditions and pulse $I^2t$, rather than a universal peak-current threshold. AC and DC interruption ratings are also different; DC has no natural periodic current zero.

Do not infer a DC rating by multiplying an AC fuse rating by √2. Eaton's fuse technology guidance distinguishes current and voltage ratings; its high-speed fuse guide discusses AC/DC application limits.

Grid connection: AC made voltage transformation straightforward with transformers and remains widely used for generation and distribution. HVDC can be advantageous for long cables, long-distance transfer and asynchronous interconnections; cable charging current and reactive exchange are major differences. Converter cost and loss, insulation, protection, conductor count and topology also matter.

A two-wire peak-limit example does not establish that every AC system is oversized or compare it fairly with three-phase transmission. See ABB's discussion of offshore HVDC.

Compare under one constraint. State the held voltage, current, insulation or conductor limit before choosing AC or DC. A benefit under one constraint may disappear under another. Use the same delivered-power requirement and loss accounting for both candidates.

7. DC steady state, periodic steady state and transients

7.1 The DC impedance interpretation

For sinusoidal steady-state analysis:

As frequency approaches zero, an ideal inductor's impedance approaches zero and a capacitor's impedance grows without bound. This gives the familiar settled DC models: inductor short circuit and capacitor open circuit, provided a bounded DC equilibrium actually exists.

The inductor can carry nonzero DC current; the capacitor can retain nonzero DC voltage. A constant voltage across an ideal inductor instead makes its current ramp forever, so that circuit has no bounded DC steady state. Similarly, constant nonzero capacitor current ramps its voltage.

7.2 Why periodic switching also has zero average inductor voltage

For a periodic state, the state variables return to the same value each period:

Integrating the component equations gives:

Therefore $\langle v_L\rangle=0$ and $\langle i_C\rangle=0$. The zero-frequency impedance interpretation is consistent with these DC components, but does not eliminate AC ripple at the switching harmonics. The entire inductor voltage is not zero in a switching converter, and the entire capacitor current is not zero.

Equality of stored energy alone is insufficient to prove a periodic signed state: +I and −I have the same inductor energy. Use repetition of current and voltage as the starting condition. In startup or another transient, the cycle-to-cycle differences are generally nonzero.

7.3 Application to an ideal buck

In continuous conduction, with approximately constant output voltage over one switching period:

The output capacitor has zero average current, so average inductor current equals average load current. Periodic balance establishes the operating point. Transfer functions later describe perturbations around it; dynamics do not disappear because the nominal operation is periodic.

8. Linearity, time invariance and the scope of a model

A linear input-output operator obeys additivity and scaling:

Time invariance means that delaying the input delays the corresponding output without otherwise changing its shape. It does not mean that the output is constant. Initial conditions must be handled consistently; fixed nonzero stored energy adds a natural response to a zero-state input-output model.

An LTI circuit can be described by an impulse response and, where the transforms exist, a transfer function. Fourier analysis also applies to signals produced by nonlinear systems. Nonlinearity prevents a general description by one input-independent linear transfer function; it does not forbid taking a Fourier transform of the resulting waveform.

A switching power converter is generally not globally LTI. A prescribed switching schedule may yield a linear time-varying circuit, while modulation, feedback and device characteristics introduce additional nonlinearities. For control design we often average over switching and linearize around a nominal operating point:

This local averaged LTI model has an operating range and frequency range, usually sufficiently below the switching frequency. Large startup excursions, saturation, mode changes and switching-frequency detail may need another model.

8.1 Why a switching simulation can be expensive

A converter combines several time scales: the switching period, the much shorter transition time, and the longer startup or control response. A 100 kHz switching frequency gives a period of 10 µs. If an edge lasts 100 ns, a maximum time step of 10 ns gives only ten intervals across that edge.

This is a starting resolution choice, not an accuracy guarantee; faster ringing may require a smaller step. Repeat with a smaller maximum step and compare the quantities that matter.

For scale, a fixed 10 ns step over 100 ms requires 10 million steps; over 10 s it requires one billion steps. Adaptive solvers do not necessarily take that many steps, because they can take larger steps between events, but repeated switching transitions and nonlinear device models still create computational work.

DC is the zero-frequency component; it does not require an infinite simulation. The required duration follows from settling time or the transient being investigated.

An edge also introduces spectral content far above the switching repetition frequency. For a 100 ns edge, 1/tr = 10 MHz is a reciprocal-time scale, not a separate oscillation or a hard bandwidth cutoff. Section 16.1 explains the different 0.35/tr bandwidth estimate for specified response shapes. The simulator must resolve the fastest relevant dynamics, not simply sample the 100 kHz repetition frequency.

Choose the model for the question: use an averaged model for slow startup/control behaviour where its assumptions hold, a switching model for ripple and commutation, and a detailed parasitic model for edge ringing or coupling. Simulate only as long as needed for that question, and distinguish the solver's internal step from the saved waveform sampling used for an FFT.

Simulation choice. Use an averaged model when the question concerns slow dynamics. It saves computation but hides individual switching events. Use a switched model when those events matter. Keep the operating mode consistent and compare a shared prediction before increasing model detail.

9. Laplace: from a differential equation to dynamics

The one-sided Laplace transform introduces a complex frequency $s=\sigma+j\omega$:

For the one-sided transform, including initial conditions:

Thus:

Initial energy must be included when solving a transient. The usual transfer-function ratio describes the zero-state response, with the other independent inputs held at zero.

The pairs and properties needed in this course fit in one table. $u(t)$ is the unit step and $a>0$.

Two limit theorems replace a full inverse transform when only the end points matter:

the second provided that all poles of $sX(s)$ lie in the left half-plane. The final-value theorem is the formal version of section 7's DC rule: as $s\to0$, $sL\to0$ (the inductor becomes a short) and $1/(sC)\to\infty$ (the capacitor becomes open). It must not be applied to an unstable or undamped response, where the limit does not exist.

Read a transfer function through its poles. A real pole at $-a$ contributes a mode $e^{-at}$ with time constant $1/a$; a complex pair $-\sigma\pm j\omega_d$ contributes a damped oscillation $e^{-\sigma t}\cos(\omega_dt+\varphi)$. A right-half-plane system mode can grow. Setting $s=j\omega$ gives the sinusoidal steady-state response when a bounded steady state exists; an algebraically finite value of H(jω) alone does not establish stability.

The averaged converter models of sections 12.2 and 12.6 are analysed through their poles and frequency responses together.

For a series R feeding a shunt C, measured across the capacitor and with no additional load:

Its pole is at −1/RC. The natural response decays with time constant τ = RC, while a step from 0 to U produces:

Check the step response with the limit theorems: $V_o(s)=U/[s(1+sRC)]$, so $sV_o(s)\to U$ as $s\to0$ (final value U) and $sV_o(s)\to0$ as $s\to\infty$ (the output starts at zero).

For a series RL circuit the current time constant is L/R. A stable first-order response settles to about 1.8% of its initial error after 4τ and 0.67% after 5τ. These percentages refer to a single exponential mode.

9.1 Why Laplace as well as Fourier? States, convergence and pole location

Fourier and Laplace describe the same dynamics from different viewpoints; Fourier is not restricted to a single sinusoid or incapable of describing transients. A decaying transient can have an ordinary Fourier transform. Fourier series describe periodic responses, while Fourier integrals describe a wider class of signals.

Initial conditions can also be represented through appropriate equivalent sources. The practical advantage of unilateral Laplace is that initial state enters the transformed differential equations explicitly.

For a constant state-space model, with no impulsive state reset at the initial instant:

The first term is the initial-state response; the second is the zero-state forced response. A transfer function alone retains only the latter input/output relation. In piecewise switching analysis, the end state of one interval becomes the initial state of the next. The time-domain form makes the same separation:

Laplace also introduces the real coordinate σ in s = σ + jω. It supplies exponential weighting and a region of convergence, not just a formal replacement of a derivative by s. For example, exp(at)u(t), with a > 0, has Laplace transform 1/(s − a) for Re(s) > a, but no ordinary Fourier transform.

Substituting jω into that rational expression lies outside its convergence region. It does not turn the growing mode into a bounded sinusoidal steady state. See Swarthmore's Laplace exponential examples.

Poles describe natural exponential modes; zeros depend on how a selected input excites a selected output and can shape phase or produce inverse response. A right-half-plane zero does not by itself make a system unstable (§16.10). For a finite-dimensional continuous-time state model, eigenvalues strictly in the left half-plane imply asymptotic internal stability.

Ideal LC poles on the imaginary axis give bounded free oscillations, but not asymptotic stability or BIBO stability: resonant forcing can grow the response. Repeated imaginary-axis modes need additional care. Hidden modes can disappear from a particular transfer function, so a cancellation must not be used to assume internal stability.

Pole placement changes A through feedback, rather than changing the transform used to inspect it. It can be derived directly in state space; Laplace and characteristic polynomials provide a compatible description. Frequency-domain feedback methods are also valid. Section 16.28 joins successive LC pulses, shifted state trajectories and a worked ideal pole-placement example. This is optional advanced reading, not additional compulsory material in the 180-minute route.

10. A switched RC: time-domain envelopes and Fourier harmonics

10.1 Define the circuit before calling it a buck without L

An ideal two-position switch alternately connects to $V_{\mathrm{in}}$ and zero. It feeds a series R and shunt C. Assume negligible loading:

The two-position switch is shown beside the continuous-input RC in section 9. The solid switch arm marks the high state; the dashed arm marks the alternative zero-volt state. They represent alternative positions, not simultaneous connections.

This is a useful dissipative PWM-to-voltage filter, resembling a buck whose energy-transfer inductance has been replaced by resistance. The low state is actively connected to zero. A switch that merely opens during the off interval is a different circuit. With a finite resistive load, the DC gain becomes $R_L/(R+R_L)$ and the time constant becomes $(R\parallel R_L)C$.

Choose $V_{\mathrm{in}}=5$ V, D = 0.4, switching frequency 100 kHz, R = 10 Ω and C = 10 µF. Then:

10.2 Exact piecewise time-domain response

During the high interval, starting at $v_{\min}$:

During the low interval, measuring local time from the falling edge:

Both intervals have the same RC time constant in this circuit. There are upper and lower cycle envelopes, rather than two independent time constants. Define:

At periodic steady state:

The example gives minimum 1.9402 V, maximum 2.0602 V, mean 2.0000 V, and ripple 119.98 mV peak-to-peak.

For cycle-start samples, starting from arbitrary $v_0$: